FeaturesDescriptionPin Assignments (Top View)Pin DescriptionsDevice OperationBurst Read AccessesBurst Write AccessesDevice Deselect (Refresh)No OperationElectrical CharacteristicsAbsolute Maximum RatingsDC Characteristics (TA = 0(C to +70(C)Power Supply Currents (TA = 0(C to +70(C, 2.4V ?? VDD ? 2.65V)AC Operating Conditions (TA = 0(C to +70(C)Timing DiagramsBurst Reads (Latency 4)Burst Writes (Latency 4)Burst Read/Write/Read (Latency 4)Deselect (Refresh) Cycle between Random ReadsPower-Up and InitializationIEEE 1149.1 Serial Boundary Scan (JTAG)Disabling the JTAG FeatureTest Access Port (TAP)TAP RegistersTAP Instruction SetMechanical DrawingsRevision LogOrdering Information72Mbit DDR ESRAM Preliminary Datasheet 2Mx36 This is a product in sampling or pre-production phase of development. Char- Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921 acteristic data and other specifications are subject to change without notice. PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com Revision 1.0C Page 1 of 27 Features • 72Mbit Density • 300 MHz Clock Rate, 600Mbps Data Rate • Low Latency Cached DRAM Architecture • Pin Selectable Read/Write Latency • Burst Length of Eight • Coherent Late Writes • Single 2.5V Power Supply • Low Power 1.5V HSTL I/O Interface • Differential Echo Clock Outputs • Programmable Output Impedance Drivers • JEDEC Standard 209-ball PBGA Package • 14 x 22 mm Body Size • 1.0 mm Ball Pitch, 11 x 19 Array • 1.65 mm (max) Package Height • 144Mb Effective Density with Clamshell Pinout Description The Enhanced Memory Systems SS2615 DDR ESRAM is a 72Mbit double data rate I/O memory device that combines a high speed HSTL signalling interface with an innovative memory architecture to optimize system price/performance in high performance cache memory and communications systems. The device is packaged in a JEDEC standard 209-ball plastic BGA. The SS2615 achieves a bandwidth of 2.7 GB/s while maintaining a low initial access of 13.3ns. The equivalent serial data rate is 21.6 Gb/s. The memory arrays are organized in sixteen independent banks, which allow a pseudo-random address cycle time of 13.3 ns. FUNCTIONAL BLOCK DIAGRAM DQA, BAA(2:0)CS#LD#R/W#ADDRESSand CONTROLDECODERS,BURSTCOUNTERSENSE AMPLIFIERSCOLUMN DECODE and READ/WRITE CACHESTIMINGGENERATORCK, CK#2Mx36MemoryArrayWORD LINE DRIVERSOUTPUT REGISTERSand BUFFERS DATALATCHESCQ,CQ#22BOUNDARYSCANTCK,TMS,TDI,TDO4DQA, BAA(2:0)CS#LD#R/W#ADDRESSand CONTROLDECODERS,BURSTCOUNTERSENSE AMPLIFIERSCOLUMN DECODE and READ/WRITE CACHESTIMINGGENERATORCK, CK#2Mx36MemoryArrayWORD LINE DRIVERSOUTPUT REGISTERSand BUFFERS DATALATCHESCQ,CQ#22BOUNDARYSCANTCK,TMS,TDI,TDO472Mbit DDR ESRAM 2Mx36 Preliminary Datasheet This is a product in sampling or pre-production phase of development. Char- Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921 acteristic data and other specifications are subject to change without notice. PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com Page 2 of 27 Revision 1.0C Pin Assignments (Top View) SS2615 2Mx36 209-ball PBGA 1 2 3 4 5 6 7 8 9 10 11 A VSS VDDQ VSS A VSS VREF VSS A VSS VDDQ VSS B DQ DQ DQ VSS A VSS A VSS NC NC NC C NC NC NC VSS A LD# A VSS DQ DQ DQ D VSS VDDQ VSS VDD A VSS A VDD VSS VDDQ VSS E DQ DQ DQ VSS BA R/W# BA VSS NC NC NC F NC NC NC VDD BA CS# BA VDD DQ DQ DQ G VSS VDDQ VSS VDD VSS VSS VSS VDD VSS VDDQ VSS H DQ DQ DQ VSS CK NC NC VSS NC NC NC J NC NC NC VSS CK# M1 NC VSS DQ DQ DQ K VSS VDDQ VSS VDD VSS VSS VSS VDD VSS VDDQ VSS L DQ DQ DQ VSS CQ VSS NC VSS NC NC NC M NC NC NC VSS CQ# VSS NC VSS DQ DQ DQ N VSS VDDQ VSS VDD VSS VSS VSS VDD VSS VDDQ VSS P DQ DQ DQ VDD ZQ NC NC VDD NC NC NC R NC NC NC VSS A NC, A A VSS DQ DQ DQ T VSS VDDQ VSS VDD VSS VSS VSS VDD VSS VDDQ VSS U DQ DQ DQ VSS A A2 A VSS NC NC NC V NC NC NC TMS A A1 A TCK DQ DQ DQ W VSS VDDQ VSS TDI VSS A0 VSS TDO VSS VDDQ VSS NOTE: Location 6R is the expansion address for a future 144Mb device.72Mbit DDR ESRAM Preliminary Datasheet 2Mx36 This is a product in sampling or pre-production phase of development. Char- Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921 acteristic data and other specifications are subject to change without notice. PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com Revision 1.0C Page 3 of 27 Pin Descriptions Symbol Type Function CK, CK# Input Input Clock: All input signals are sampled on the rising edge of CK and the falling edge of CK#, where CK and CK# voltage levels cross. CS# Input Chip Select: This active low synchronous input is registered when LD# is low, otherwise ignored. When LD# is registered low and chip select is registered low, the chip begins a read or write cycle. When LD# is registered low and chip select is registered high, the chip begins a deselect cycle. LD# Input Load Address: Active low LD# latches the address, and decodes the R/W#. When LD# is registered high, the device internally increments the A(2:0) address that was initially latched. R/W# Input Read/Write Input: This signal determines whether to start a read or write cycle only when both CS# and LD# are registered low. A(2:0) Input Burst Address Inputs: These inputs are registered when CS# and LD# are low, otherwise they are ignored. They define the starting address. The burst wrap sequence is defined in the Burst Wrap Sequence Table. A, BA Input Address Inputs: These address inputs are registered when CS# and LD# are low, otherwise they are ignored. The BA bank address pins determine which one of the sixteen internal banks is accessed. DQ Input/ Output Data I/O: Data bus inputs and outputs. For read cycles, the device drives output data on these pins after the read latency is satisfied. Read data is edge aligned with the output clocks CQ and CQ#. At the completion of the burst read cycle, the device automatically places the output buffers in hi-Z. For write cycles, input data is applied to these pins and must be set-up and held relative to the rising and falling edge of clock CK. CQ, CQ# Output Output Clock: These free running output clocks are used to capture read data at the memory controller using CQ and CQ# as a