Heading - Wires Part II and SignallingHeading - Voltage and Current Mode IHeading - Voltage and Current Mode IIHeading - “Wired Or” BusHeading - Capacitive Termination IHeading - Capacitive Termination IIHeading - What is a Stub?Heading - Series Stub Terminated LogicHeading - Rambus SignallingHeading - ODT: On Die TerminationHeading - Input Buffering - References IHeading - Input Buffering - References IIHeading - Differential SignallingHeading - Crosstalk IHeading - Crosstalk IIDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 1Wires Part II and SignallingZLZSVI Z0VS VL - More on transmission lines- Termination- CrosstalkZLZSVI Z0VS VLDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 2Voltage and Current Mode I- Current and voltages at output controlled by carefuldesign of resistors valuesMOSFETBJTIbase- BJT: Current controlled current source- MOSFET: Voltage controlled current source+-- “On resistance” of MOSFET is low. “Off resistance”of MOSFET is high- “resistance” through BJT is always highDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 3Voltage and Current Mode II- “1” and “0” represented by +/- of voltage or currentZ0ITZGTTGNDZ0VTZRTTGND+-VT = IT Z0“Current Mode”“Voltage Mode”- Receiver sees voltage differential.from transmitter prespective- No “pure” voltage-mode or current mode. - ZGT is high. Isolates circuit from noise on power planes.ZoutZoutZout << Z0- If Zout >> Z0, current mode. Zout << Z0, voltage modeZout >> Z0DRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 4“Wired Or” Bus- Terminating resistor supplies “1”, voltage on bus isRterm- Driver sinks current to Vssq when it needs to drive “0”equal to Vddq when no driver is active- Power consumed when “driving 0” and active currentRtermVddqVddqVssqVssqVssqdrivers“drive 0”terminator“supplies 1”sinksDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 5Capacitive Termination IZLZSVI Z0VS VL - Capacitors behave like short circuit whenZL = 0; Short Circuitρρρρ = 0 - ZS0 + ZSρρρρ = -1ZL = inf; Open Circuitρρρρ = ZLZLρρρρ = 1not charged. Once charged, behaves likeopen circuit.DRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 6Capacitive Termination IIZLZSVI Z0VS VL VL VL VSVS- When “shorted”, VS is reflected with the same magnitude back toward source.- The “magnitude” here is the “magnitude” timetime- To minimize glitch, limit slew rate.of rise time.DRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 7What is a Stub?Z0 = 50 ΩΩΩΩGND5nH2 pF0.2 pF75ΩΩΩΩ50 ΩΩΩΩtrace50ΩΩΩΩpkgbondwirepad& rxStub- Signal path inside of package also significanttraceterminatingresistorDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 8Series Stub Terminated LogicZ0 = 50 ΩΩΩΩGND5nH2 pF0.2 pFbondwirepad& rxseriesresistorReflection Coefficient = ρρρρ = ZL - ZSZL + ZS25 ΩΩΩΩρρρρ = 25 - 5025 + 50= - 0.3333- Series resistor isolates stub from line- reduces ringing- reduces powerCDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 9Rambus SignallingControllerdrdramclockturnsaroundchipdrdramchipdrdramchipterminationtermination- Controller sends full height signal swings- DRAM chips send half height signal swings- Reflection off of controller driver ~open circuitterminatedcreates full height signal swing- Current mode- Current control and voltage slewrate controlDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 10ODT: On Die TerminationVddq VddqVssqVssqDRAM inputbufferSW1SW1SW2SW2Rval1Rval1Rval2Rval2DRAMDQ inputpin- Active, dynamic termination, depending on R/W, andnumber of loads on electrical bus- Can be turned on/off in 2 cycles, off in 2.5 cycles- Designed into DDR IIDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 11Input Buffering - References IVoutVin3.33.02.01.02.01.03.0 3.3input voltageVin low = 0.8VVin high = 2.0VVout high = 2.4VVout low = 0.4VLVTT LoutputvoltageinverterSimple InverterinputvoltageoutputvoltageVoutVin2.52.01.02.01.02.5input voltageVin low = Vout low = 0.373VSSTL-2outputvoltageinverterVref - 0.15vVin High = Vref + 0.15v(full current drive)Vout low = Vddq - 0.373V(full current drive)inputvoltageoutputvoltagevrefDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 12Input Buffering - References IIvrefVccGndvoutvin- Local or remote reference?- Inverters aren’t very good for high frequency signallingvin0v0vin1vin2vin3v1v2v3DRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 13Differential Signalling- The complement signal path is the current return path- Send the signal and its complementvin0 +v0vin1 +vin2 +vin3 +v1v2v3vin0 -vin1 -vin2 -vin3 -- Signal pairs must be routed closely together- Signalling scheme can reject common mode noisequite wellDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 14Crosstalk I- Magnitude of crosstalk depends on current magnitude- Signals should couple to ground to minimize EM.Into the boardout of the boardsignal tracesGnd plane- If EM fields do not cancel, could induce voltage/currentexcitation in nearby victim line.current loop area(s) AND signal patterns on “aggressor”linesDRAM MemorySystem: Lecture 9Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 15Crosstalk II- Routing of wires done for path length matching may in fact have slightly different “electrical distance” due to segments of the wire coupling to