Advance Information Rambus® 32 and 64 bit RIMM™ ModuleTechnology SummaryVersion Number: 0.0Date: June 2001Document Number: Advance InformationRambus 32 and 64 bit RIMM™ Module 2Technology SummaryAdvance InformationCopyright © June 2001, Rambus Inc. All rights reserved.No part of this document may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means without the prior written permission of Rambus Inc.Rambus, RDRAM, and the Rambus Logo are registered trademarks of Rambus Inc. Direct Rambus, Direct RDRAM, QRSL, RIMM, and SO-RIMM are trademarks of Rambus Inc.Rambus Inc. assumes no responsibility or liability for any use of the information contained herein. Rambus components are manufactured and sold by Rambus partners. Rambus partners provide data sheets spe-cific to their products. For a list of Rambus partners who are providing Rambus components, refer to the Partner Pavilion page on our website: http://www.rambus.com.Data contained in this document is preliminary and subject to change without notice. Rambus Inc. assumes no responsibility for any errors that may appear in this document. Rambus Inc. makes no warran-ties, express or implied, of functionality or suitability for any purpose. No license is granted by its implica-tion or otherwise under any patent or patent rights of Rambus Inc.Rambus Inc. 4440 El Camino RealLos Altos, California USA 94022Telephone: 650-947-5000Fax: 650-947-5001Rambus 32 and 64 bit RIMM™ Module 3Technology SummaryAdvance InformationIntroductionThroughout the 15-year history of DRAM memory modules, two avenues have been used to increase the bandwidth supplied from a memory module: increased width and frequency. In the late 1980s, DRAMs were packaged on an 8 bit wide SIMM with up to eight components on a module. The evolution of DRAM modules led to 32 bit SIMMs that used page mode and EDO devices, followed by the more recent SDRAM DIMM with a data path width of 64 bits. In 1999, Rambus® DRAM (RDRAM®) memory technology introduced an 8x increase over the pervasive PC100 in memory system operating frequency. This dramatic increase in data rate paved the way for the 16 bit wide RIMM. The 16 bit wide RIMM had the first-ever decrease in module and chipset interface data width while doubling the module bandwidth. Just as previous memory technologies used increased data width to allow increased module band-width, RIMM modules can provide a similar increase in width to provide increased module and system bandwidth without requiring major changes in DRAM devices or controllers connecting to them.Figure 1: Module Data Width History 8/9Data Width (bits)16/1832/3664/728 bitSIMM32 bit SIMM 64 bitDIMM16 bit RIMM32 bit RIMM 64 bit RIMM EDOSDRAMRDRAMRambus 32 and 64 bit RIMM™ Module 4Technology SummaryAdvance InformationTechnology SummaryIn addition to the increased width, these RIMM modules will support a range of data frequencies. As shown in Table 1 all of RIMM modules support both 800 MHz and 1066 MHz operations. These operating frequencies are ideally suited for systems operating with base frequencies of 100 MHz and 133 MHz respectively. Table 1 also summarizes the features and technologies provided for various width modules.Table 1: RIMM Technology Summary.All RIMM modules use the conventional RDRAM and RSL signaling. In order to better understand the architecture of the 32 and 64 bit RIMM modules, a basic understanding of RDRAM and Rambus Signaling is necessary. As shown in Figure 2, the interface to the RDRAM device is basically composed of two high speed buses: the request bus (RQ) and the data bus (DQ). A slower CMOS bus is used for initialization and power management. For a more detailed description of the operation of the RDRAM device, refer to the RDRAM datasheet. The request bus is an 8 bit bus used to communicate control and address information from the controller to the RDRAM device and is sampled synchronously by the RDRAM device with the ClockFromMaster differential clock pair. The data bus is a 16 bit wide bus (18 for ECC systems) that carries data to and from the RDRAM device for writes and reads respectively. The data bus is sometimes referred to as being two bytes wide, with one byte called the “A byte” and the second, the “B byte”. Write data travels from the controller to the RDRAM device across the data bus and sampled synchronously with the ClockFromMaster differential clock pair. Read data is transmitted from the RDRAM device to the controller on the data bus and transmitted by the RDRAM device synchronously, with the dif-ferential clock travelling in the same direction—ClockToMaster. This clock is then used at the controller for sam-pling the read data.The request bus and the data bus are routed as transmission lines with the bus passing by the RDRAM devices before terminating at the end of the bus opposite the controller. The termination is achieved through a pull-up resistor to the termination voltage Vterm. This termination resistor is matched to the effective impedance of the bus after the effects of the device loading and routing are included.Module TypeModule Name RIMM1600 RIMM2100 RIMM3200 RIMM4200 RIMM6400 RIMM8500RDRAM Data Frequency 800 MHz 1066 MHz 800 MHz 1066 MHz 800 MHz 1066 MHzModule Data Width 16 or 18 bits 16 or 18 bits 32 or 36 bits 32 or 36 bits 64 or 72 bits 64 or 72 bitsModule BW in MB/s 1600 2133 3200 4266 6400 8532Minimum Device Capacity 112244Maximum Device Capacity 16 16 16 16 16 16Request busses 112211Shared Request Bus No No No No Yes YesPartial Data Termination No No Yes Yes Yes YesByte masking suppport Yes Yes Yes Yes No NoECC module width 181836367272Module pin count 168 168 184 184 326 326Data bus impedance 28 Ohms 28 Ohms 40 Ohms 40 Ohms 40 Ohms 40 OhmsModule Vdd 2.5 Volts 2.5 Volts 2.5 Volts 2.5 Volts 1.8 Volts 1.8 VoltsModule Vterm none none 1.8 Volts 1.8 Volts 1.5 -1.8 Volts 1.5 -1.8 VoltsMesochronous Write Data No No No No Yes Yes16 bit RIMMs 32 bit RIMMs 64 bit RIMMs232232Rambus 32 and 64 bit RIMM™ Module 5Technology SummaryAdvance InformationFigure 2: RDRAM System ArchitectureThe CMOS bus is a slower speed bus used primarily for initialization. It comprises a serial chain of SIn and SOut sequencing in daisy chain between devices, A clock, SCK, and a command signal. The command signal, CMD, is routed as a bus to the device, signals commands and is used for timing generation.. 16 bit RIMM ArchitectureIn a 16 bit RIMM system, the request