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Title PageContentsRevision HistoryIntroduction 11.1 Terminology1.2 Related Documents1.3 Intel® 875P Chipset System Overview1.4 Intel® 82875P MCH Overview1.4.1 Host Interface1.4.2 System Memory Interface1.4.3 Hub Interface1.4.4 Communications Streaming Architecture (CSA) Interface1.4.5 AGP Interface1.5 Clock RatiosSignal Description 22.1 Host Interface Signals2.2 Memory Interface2.2.1 DDR DRAM Interface A2.2.2 DDR DRAM Interface B2.3 Hub Interface2.4 CSA Interface2.5 AGP Interface Signals2.5.1 AGP Addressing Signals2.5.2 AGP Flow Control Signals2.5.3 AGP Status Signals2.5.4 AGP Strobes2.5.5 PCI Signals–AGP Semantics2.5.5.1 PCI Pins During PCI Transactions on AGP Interface2.6 Clocks, Reset, and Miscellaneous2.7 RCOMP, VREF, VSWING2.8 Power and Ground Signals2.9 MCH Sequencing Requirements2.10 Signals Used As Straps2.10.1 Functional Straps2.10.2 Strap Input Signals2.10.3 Test Mode Straps2.11 Full and Warm Reset StatesRegister Description 33.1 Register Terminology3.2 Platform Configuration Structure3.3 Routing Configuration Accesses3.3.1 Standard PCI Bus Configuration Mechanism3.3.2 PCI Bus 0 Configuration Mechanism3.3.3 Primary PCI and Downstream Configuration Mechanism3.3.4 AGP/PCI_B Bus Configuration Mechanism3.4 I/O Mapped Registers3.4.1 CONFIG_ADDRESS—Configuration Address Register3.4.2 CONFIG_DATA—Configuration Data Register3.5 DRAM Controller/Host-Hub Interface Device Registers (Device 0)3.5.1 VID—Vendor Identification Register (Device 0)3.5.2 DID—Device Identification Register (Device 0)3.5.3 PCICMD—PCI Command Register (Device 0)3.5.4 PCISTS—PCI Status Register (Device 0)3.5.5 RID—Revision Identification Register (Device 0)3.5.6 SUBC—Sub-Class Code Register (Device 0)3.5.7 BCC—Base Class Code Register (Device 0)3.5.8 MLT—Master Latency Timer Register (Device 0)3.5.9 HDR—Header Type Register (Device 0)3.5.10 APBASE—Aperture Base Configuration Register (Device 0)3.5.11 SVID—Subsystem Vendor Identification Register (Device 0)3.5.12 SID—Subsystem Identification Register (Device 0)3.5.13 CAPPTR—Capabilities Pointer Register (Device 0)3.5.14 AGPM—AGP Miscellaneous Configuration Register (Device 0)3.5.15 GC—Graphics Control Register (Device 0)3.5.16 CSABCONT—CSA Basic Control Register (Device 0)3.5.17 EAP—DRAM Error Data Register (Device 0)3.5.18 DERRSYN—DRAM Error Syndrome Register (Device 0)3.5.19 DES—DRAM Error Status Register (Device 0)3.5.20 FPLLCONT— Front Side Bus PLL Clock Control Register (Device 0)3.5.21 PAM[0:6]—Programmable Attribute Map Registers (Device 0)3.5.22 FDHC—Fixed Memory(ISA) Hole Control Register (Device 0)3.5.23 SMRAM—System Management RAM Control Register (Device 0)3.5.24 ESMRAMC—Extended System Management RAM Control Register (Device 0)3.5.25 ACAPID—AGP Capability Identifier Register (Device 0)3.5.26 AGPSTAT—AGP Status Register (Device 0)3.5.27 AGPCMD—AGP Command Register (Device 0)3.5.28 AGPCTRL—AGP Control Register (Device 0)3.5.29 APSIZE—Aperture Size Register (Device 0)3.5.30 ATTBASE—Aperture Translation Table Register (Device 0)3.5.31 AMTT—AGP MTT Control Register (Device 0)3.5.32 LPTT—AGP Low Priority Transaction Timer Register (Device 0)3.5.33 TOUD—Top of Used DRAM Register (Device 0)3.5.34 MCHCFG—MCH Configuration Register (Device 0)3.5.35 ERRSTS—Error Status Register (Device 0)3.5.36 ERRCMD—Error Command Register (Device 0)3.5.37 SMICMD—SMI Command Register (Device 0)3.5.38 SCICMD—SCI Command Register (Device 0)3.5.39 SKPD—Scratchpad Data Register (Device 0)3.5.40 CAPREG—Capability Identification Register (Device 0)3.6 PCI-to-AGP Bridge Registers (Device 1)3.6.1 VID1—Vendor Identification Register (Device 1)3.6.2 DID1—Device Identification Register (Device 1)3.6.3 PCICMD1—PCI Command Register (Device 1)3.6.4 PCISTS1—PCI Status Register (Device 1)3.6.5 RID1—Revision Identification Register (Device 1)3.6.6 SUBC1—Sub-Class Code Register (Device 1)3.6.7 BCC1—Base Class Code Register (Device 1)3.6.8 MLT1—Master Latency Timer Register (Device 1)3.6.9 HDR1—Header Type Register (Device 1)3.6.10 PBUSN1—Primary Bus Number Register (Device 1)3.6.11 SBUSN1—Secondary Bus Number Register (Device 1)3.6.12 SUBUSN1—Subordinate Bus Number Register (Device 1)3.6.13 SMLT1—Secondary Bus Master Latency Timer Register (Device 1)3.6.14 IOBASE1—I/O Base Address Register (Device 1)3.6.15 IOLIMIT1—I/O Limit Address Register (Device 1)3.6.16 SSTS1—Secondary Status Register (Device 1)3.6.17 MBASE1—Memory Base Address Register (Device 1)3.6.18 MLIMIT1—Memory Limit Address Register (Device 1)3.6.19 PMBASE1—Prefetchable Memory Base Address Register (Device 1)3.6.20 PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)3.6.21 BCTRL1—Bridge Control Register (Device 1)3.6.22 ERRCMD1—Error Command Register (Device 1)3.7 PCI-to-CSA Bridge Registers (Device 3)3.7.1 VID3—Vendor Identification Register (Device 3)3.7.2 DID3—Device Identification Register (Device 3)3.7.3 PCICMD3—PCI Command Register (Device 3)3.7.4 PCISTS3—PCI Status Register (Device 3)3.7.5 RID3—Revision Identification Register (Device 3)3.7.6 SUBC3—Class Code Register (Device 3)3.7.7 BCC3—Base Class Code Register (Device 3)3.7.8 MLT3—Master Latency Timer Register (Device 3)3.7.9 HDR3—Header Type Register (Device 3)3.7.10 PBUSN3—Primary Bus Number Register (Device 3)3.7.11 SBUSN3—Secondary Bus Number Register (Device 3)3.7.12 SMLT3—Secondary Bus Master Latency Timer Register (Device 3)3.7.13 IOBASE3—I/O Base Address Register (Device 3)3.7.14 IOLIMIT3—I/O Limit Address Register (Device 3)3.7.15 SSTS3—Secondary Status Register (Device 3)3.7.16 MBASE3—Memory Base Address Register (Device 3)3.7.17 MLIMIT3—Memory Limit Address Register (Device 3)3.7.18 PMBASE3—Prefetchable Memory Base Address Register (Device 3)3.7.19 PMLIMIT3—Prefetchable Memory Limit Address Register (Device 3)3.7.20 BCTRL3—Bridge Control Register (Device 3)3.7.21 ERRCMD3—Error Command Register (Device 3)3.7.22 CSACNTRL—CSA Control Register (Device 3)3.8 Overflow Configuration Registers (Device 6)3.8.1 VID6—Vendor Identification Register (Device 6)3.8.2 DID6—Device Identification Register (Device 6)3.8.3 PCICMD6—PCI Command Register (Device 6)3.8.4 PCISTS6—PCI Status Register (Device 6)3.8.5 RID6—Revision Identification Register (Device 6)3.8.6 SUBC6—Sub-Class Code Register (Device 6)3.8.7 BCC6—Base Class Code Register (Device 6)3.8.8 HDR6—Header Type


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UMD ENEE 759H - Intel 875P Chipset

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