HIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 1 Calculating Power for (Micron) DDR SDRAMs (Stolen from Micron DesignLine , vol. 10, no. 2, 2001) Organization of 128Mb DDR SDRAM: HIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 2 Current Profile: CKE CKE Turns on DRAM device:CKE Low: “Power-Down”CKE High: “Power-Down” CKE must be high for active operation, including auto-refreshHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 3 Idle and Operating Currents V DD = +2.5V ±0.2V … use max=2.7V for Power Parameter/Condition SymbolMicron 128Mb DDR-133Infineon 256Mb DDR-200Fujitsu 256Mb FCRAMInfineon 512Mb DDR-200 Operating Current I DD 0 105 70 60 125Precharge Power-Down Standby Current I DD 2P 3528Idle Standby Current I DD 2F 45 30 35 30Active Power-Down Standby Current I DD 3P 18 13 ??? 11Active Standby Current I DD 3N 45 40 35 40READ Current BL=2 I DD 4R 110 79 170 135WRITE Current BL=2 I DD 4W 110 85 170 130Auto Refresh Current(Self-Refresh?) I DD 5 5 1.5 3 2.5 HIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 4 Operating Current: I DD 0 AVERAGE OPERATING CURRENT(Continuous Activate-Precharge: Refresh)... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 5 Precharge Power-Down: I DD 2P CKE Low, All Banks Precharged... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn Decoder HIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 6 Idle Standby Current: I DD 2F CKE High, All Banks Precharged... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 7 Active Power-Down: I DD 3P CKE Low, At Least One Bank Active... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn Decoder HIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 8 Active Standby Current: I DD 3N CKE High, At Least One Bank Active... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderHIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 9 READ Current: I DD 4R Continuous Burst from Active Bank(does not include I/O)... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn Decoder HIGH-SPEEDMEMORY SYSTEMS Spring 2003Bruce Jacob David WangUniversity of Maryland Lecture 18 SLIDE 10 WRITE Current: I DD 4W Continuous Burst to Active Bank(does not include I/O)... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 11Auto Refresh Current: IDD5AVERAGE COST of PRECHARGE(assumes minimum overhead)... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderOnly on duringactual refresh eventsHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 12Power: p(ACT) = ACT+PRE• [IDD0 - IDD3N] * VDD = [105mA - 45mA] * 2.7V = 162mWHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 13Power: p(ACT) scaled I• [IDD0 - IDD3N] * * VDD = 130mWRCtACTn * CKt---------------------------------HIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 14Power: p(ACT) scaled II• Interleaved banks = 2x maximum ACT rate = 324mWHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 15Power: p(WR) = move data• [IDD4W - IDD3N] * * VDD = 50mWnum of WR cyclesACTn---------------------------------------------------HIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 16p(WR)+p(ACT)+p(ACT_STBY)• p(WR) = [IDD4W - IDD3N] * * VDD• = [110mA - 45mA] * * 2.7V • = 50mW• p(ACT) = [IDD0 - IDD3N] * * VDD• = (105mA - 45mA) * * 2.7V• = 93mW• p(ACT_STBY) = IDD3N * VDD = 122mWp(TOT) = 265mWnum of WR cyclesACTn---------------------------------------------------4CK14CK----------------RCtACTn * CKt---------------------------------60ns14CK * 7.5nsCK-------------------------------------------------HIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 17Power: p(RD) = move data• [IDD4R - IDD3N] * * VDD num of RD cyclesACTn--------------------------------------------------HIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 18p(RD)+p(ACT)+p(ACT_STBY)• p(RD) = [IDD4R - IDD3N] * * VDD• = [110mA - 45mA] * * 2.7V • = 50mW• p(ACT) = [IDD0 - IDD3N] * * VDD• = (105mA - 45mA) * * 2.7V• = 93mW• p(ACT_STBY) = IDD3N * VDD = 122mWBut wait, there’s more …num of RD cyclesACTn--------------------------------------------------4CK14CK----------------RCtACTn * CKt---------------------------------60ns14CK * 7.5nsCK-------------------------------------------------HIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 19Power: p(DQ)IDD4R typically assumes IOUT = 0mAMust Calculate IOUT & VOUT • VOUT = 1.25V - [ IOUT * (RSER + RTERM) ]• VOUT = 1.25V - [ 16.8mA * (22 OHM + 28 OHM) ]• VOUT = 0.41VHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 20Power: p(DQ) IIp(per DQ) = VOUT * IOUTp(per DQ) = 0.41V * 16.8mA = 6.88mW• p(DQ) = p(perDQ) * (numDQ + numDQS) * Assume x8 partp(DQ) = 6.88mW * (8 + 1) * p(DQ) = 17.7mWnum of RD cyclesACTn--------------------------------------------------4CK14CK---------------HIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 21Power: p(RD) including DQ• p(TOT) = 50mW + 93mW + 122mW + 18mW = 283mWHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 22Scaling of ParametersHIGH-SPEEDMEMORYSYSTEMSSpring 2003Bruce JacobDavid WangUniversity ofMarylandLecture 18SLIDE 23Comparison Parameter/Condition SymbolMicron 128Mb DDR-133Infineon 256Mb