A Case Study: 3D DRAMENEE 759H Spring 2003Amol GoleGunjan DangSumod PawgiMemory Wallß The rate of improvementin microprocessor speedexceeds that of DRAM:Processor – MemoryPerformance GapSPEEDYearsCPUDRAMMemory SystemMemory Access Latencyß Trend to move Memory Controller on-chipß Interface between MC and DRAM has an access latency of up to 2ns. ß Forms significant portion of total access time as DRAM technology improvesMemory Bandwidthß Amount of data that is transferred in eachaccess (Mb/s)ß Bus Widthß Pin limitedß Bus Frequencyß Signaling issuesSignalingß RC model works for on-chip wires and theLC model for PC board wiresß Power Supply NoiseDistanceSingle Supply Noise (mV)On-chip, local bus, 30um10On-chip, global bus, 1mm50On-chip, global bus, 7mm350Between chips on a PCB250Between PCB, 1m500More Signaling issuesß Cross talkß Intersymbol Interferenceß Timing Noiseß Timing Closureß I/O Buffersß Skin effectß SO WHAT SHOULD WE DO????3D DRAMß Place wafers on top ofone anotherß Vias complete pathsbetween differentwafers through smallpads on the wafersCPUDRAM3D IC Structure12um12umPad2umPadViaActive LayerSubstrateSubstrate300um300um15umAdvantagesß Pin count is reducedß Smaller pads (lower capacitance) used in the 3Dtechnology result in faster bus between DRAM and CPUß Higher bandwidth because of less constraint on data buswidthß On-chip capacitive loading much smaller => lower powerdissipationß The latency is reducedß Fast bus between the CPU and DRAMß Parallel decoding of address lines => smaller address setup timeß Extra control lines availableß NEC - 3.5ns access times!!Why not eDRAM?ß eDRAM = on-chip DRAMß Monolithicß DRAM-based or Logic-based designß eDRAM - 20-50% of dieareaThis is why!ß Less limitation on die sizeß More space to fit memoryß Large applications will not lower performanceß Difficult to use logic process technology to makeeDRAM.ß 3D DRAM can be built using existing DRAM-based designs.ß Easier routing and reduced wire lengthsLimitationsß Fabrication technology is underdevelopmentß IBM’s wafer-level bonding approachß Costs are running highß Thermal coupling between neighboringlines => self heating of interconnect linesß Cannot upgrade memoryß Not for general purpose computersFuture Workß Development of cheaper fabricationtechniquesß Study on 3D DRAM replacing L2/L3 cacheß Designing better DRAM structures whichexploit the vertical dimensionß Access each DRAM cell
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