1Heading - Overview1Heading - FeaturesFigure - Figure 1: 1066 MHz RDRAM‚ CSP Package1Heading - Key Timing Parameters/Part Numbers1Heading - Related Documentation1Heading - Pinouts and Definitions2Heading - Center-Bonded Devices - PreliminaryTableTitle - Table 1: Center Bonded Device (top view)TableTitle - Table 2: Pin DescriptionFigure - Figure 2: 256/288 Mb ((512Kx16/18x32s)) RDRAM Devi...1Heading - General Description1Heading - Packet FormatTableTitle - Table 3: Field Description for ROWA Packet and ROW...TableTitle - Table 4: Field Description for COLC Packet, COLM P...Figure - Figure 3: Packet Formats1Heading - Field Encoding SummaryTableTitle - Table 5: Device Field Encodings for ROWA Packet an...TableTitle - Table 6: ROWA Packet and ROWR Packet Field Encodin...TableTitle - Table 7: COLC Packet Field EncodingsTableTitle - Table 8: COLM Packet and COLX Packet Field Encodin...1Heading - DQ Packet TimingFigure - Figure 4: Read (Q) and Write (D) Data Packet - Tim...1Heading - COLM Packet to D Packet MappingFigure - Figure 5: Mapping Between COLM Packet and D Packet...1Heading - ROW-to-ROW Packet InteractionFigure - Figure 6: ROW-to-ROW Packet Interaction- TimingTableTitle - Table 9: ROW-to-ROW Packet Interaction - Rules1Heading - ROW-to-ROW Interaction - continued1Heading - ROW-to-COL Packet InteractionFigure - Figure 7: ROW-to-COL Packet Interaction- TimingTableTitle - Table 10: ROW-to-COL Packet Interaction - Rules1Heading - COL-to-COL Packet InteractionFigure - Figure 8: COL-to-COL Packet Interaction- TimingTableTitle - Table 11: COL-to-COL Packet Interaction - Rules1Heading - COL-to-ROW Packet InteractionFigure - Figure 9: COL-to-ROW Packet Interaction- TimingTableTitle - Table 12: COL-to-ROW Packet Interaction - Rules1Heading - ROW-to-ROW ExamplesFigure - Figure 10: Row Packet ExampleFigure - Figure 11: Row Packet ExampleFigure - Figure 12: Row Packet Examples1Heading - Row and Column Cycle Description1Heading - Precharge MechanismsFigure - Figure 13: Precharge via PRER Command in ROWR Pack...Figure - Figure 14: Offsets for Alternate Precharge Mechani...1Heading - Read Transaction - ExampleFigure - Figure 15: Read Transaction Example1Heading - Write Transaction - ExampleFigure - Figure 16: Write Transaction Example1Heading - Write/Retire - ExamplesFigure - Figure 17: Normal Retire (left) and Retire/Read Or...1Heading - Write/Retire Examples - continuedFigure - Figure 18: Retire Held Off by Read (left) and Cont...Figure - Figure 19: Retire Held Off by Reads to Same Device...1Heading - Interleaved Write - ExampleFigure - Figure 20: Interleaved Write Transaction with Two ...1Heading - Interleaved Read - Example1Heading - Interleaved RRWW - ExampleFigure - Figure 21: Interleaved Read Transaction with Two D...Figure - Figure 22: Interleaved RRWW Sequence with Two Dual...1Heading - Control Register TransactionsFigure - Figure 23: Serial Write (SWR) Transaction to Contr...Figure - Figure 24: Serial Read (SRD) Transaction Control R...1Heading - Control Register PacketsFigure - Figure 25: SETR, CLRR,SETF TransactionTableTitle - Table 13: Control Register Packet FormatsTableTitle - Table 14: Field Description for Control Register P...1Heading - InitializationFigure - Figure 26: SIO Reset Sequence1Heading - Control Register SummaryTableTitle - Table 15: Control Register Summary (Continued)Figure - Figure 27: INIT RegisterFigure - Figure 28: CNFGA RegisterFigure - Figure 29: CNFGB RegisterFigure - Figure 30: TEST RegisterFigure - Figure 31: DEVID RegisterFigure - Figure 32: REFB RegisterFigure - Figure 33: CCA RegisterFigure - Figure 34: REFR RegisterFigure - Figure 35: CCB RegisterFigure - Figure 36: NAPX RegisterFigure - Figure 37: PDNXA RegisterFigure - Figure 38: PDNX RegisterFigure - Figure 39: TPARM RegisterFigure - Figure 40: TFRM RegisterFigure - Figure 41: TCDLY1 RegisterFigure - Figure 42: SKIP RegisterFigure - Figure 43: TEST RegistersFigure - Figure 44: TCYCLE RegisterFigure - Figure 45: Control Register1Heading - Power State ManagementTableTitle - Table 16: Power State SummaryFigure - Figure 46: Power State Transition DiagramFigure - Figure 47: STBY Entry (left) and STBY Exit (right)...Figure - Figure 48: NAP Entry (left) and PDN Entry (right)Figure - Figure 49: NAP and PDN ExitFigure - Figure 50: NAP Entry/Exit Windows (left) and PDN E...1Heading - Refresh1Heading - Refresh (continued)Figure - Figure 51: REFA/REFP Refresh Transaction ExampleFigure - Figure 52: NAP/PDN Exit - tBURST Requirement1Heading - Current and Temperature ControlFigure - Figure 53: Current Control CAL/SAM Transaction Exa...Figure - Figure 54: Temperature Calibration (TCEN-TCAL) Tra...1Heading - Timing ConditionsTableTitle - Table 17: Timing ConditionsTableTitle - Table 18: Electrical Conditions1Heading - Timing CharacteristicsTableTitle - Table 19: Timing Characteristics1Heading - Electrical CharacteristicsTableTitle - Table 20: Electrical Characteristics1Heading - RSL - ClockingFigure - Figure 55: RSL Timing - Clock Signals1Heading - RSL - Receive TimingFigure - Figure 56: RSL Timing - Data Signals for Receive1Heading - RSL - Transmit TimingFigure - Figure 57: RSL Timing - Data Signals for Transmit1Heading - CMOS - Receive TimingFigure - Figure 58: CMOS Timing - Data Signals for ReceiveFigure - Figure 59: CMOS Timing - Device Address for NAP or...1Heading - CMOS - Transmit TimingFigure - Figure 60: CMOS Timing - Data Signals for Transmit...1Heading - RSL - Domain Crossing WindowFigure - Figure 61: RSL Transmit - Crossing Read Domains1Heading - Timing ParametersTableTitle - Table 21: Timing Parameter Summary1Heading - Absolute Maximum RatingsTableTitle - Table 22: Absolute Maximum Ratings1Heading - IDD - Supply Current ProfileTableTitle - Table 23: Supply Current ProfileTableTitle - Table 24: Supply Current at Initialization1Heading - Capacitance and InductanceFigure - Figure 62: Equivalent Load Circuit for RSL PinsTableTitle - Table 25: RSL Pin ParasiticsTableTitle - Table 26: CMOS Pin Parasitics1Heading - Center-Bonded uBGA Package (16x6)Figure - Figure 63: Center-Bonded uBGA PackageTableTitle - Table 27: Center-Bonded uBGA Package Dimensions1Heading - Interleaved Device ModeFigure - Figure 64: ACT, PRE, RD, and WR Commands for Eight...Figure - Figure 65: Mapping from DEVID2..0 and DC2..0 Field...Figure - Figure 66: Mapping from DEVID2..0 and DC2..0 Field...1Heading - Table Of ContentsDocument DL-0118-06 Version 0.6 Advance Information Page 1Advance Information800/1066 MHz