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Rev. 0.52/Nov. 02 1 HY5PS12423(L)F HY5PS12823(L)FHY5PS121623(L)F512Mb DDR-II SDRAMHY5PS12423(L)FHY5PS12823(L)FHY5PS121623(L)FRev. 0.52/Nov. 02 2 HY5PS12423(L)F HY5PS12823(L)FHY5PS121623(L)FREVISION HISTORYRevision No.Revision DatePage of RevsionDescription of Change0.2 June.02 page3 added tCK on the operating frequency table0.3 July.02 All Changed master page0.4 Aug.02 All corrected typos and change some descriptions 0.5 Aug.02 All corrected typos and wrong definiotions and changed some items0.51 Oct.02 Page7,52 page7:modify Package Dimension, page52 change TA to TC, etc.0.52 Nov.02 corrected typos, Add x16 part and update Package dimensions0.53 Dec.02 Page1,6,7,29corrected typos and delete page29 tRAS programming definitionRev. 0.52/Nov. 02 3 HY5PS12423(L)F HY5PS12823(L)FHY5PS121623(L)FKEY FEATURES Preliminary• VDD = 1.8V, 2.5V (Optional) • VDDQ = 1.8V +/- 0.1V• All inputs and outputs are compatible with SSTL_18 interface• Fully differential clock inputs (CK, /CK) operation• Double data rate interface• Source synchronous - data transaction aligned to bidirectional data strobe (DQS, DQS)• Differential Data Strobe (DQS, DQS)• Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)• On chip DLL align DQ, DQS and DQS transition with CK transition• DM mask write data-in at the both rising and falling edges of the data strobe• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock• Programmable CAS latency 3, 4 and 5 supported• Programmable Additive latency 0, 1, 2, 3, 4 and 5 supported• Programmable burst length 4 / 8 with both nibble sequential and interleave mode• Internal four bank operations with single pulsed RAS• Auto refresh and self refresh supported• Programmable tRAS supported• 8K refresh cycles / 64ms• JEDEC standard 60ball FBGA(x4/x8) & 84bal FBGA(x16)l• Full strength driver option controlled by EMRS• On Die Termination supported• Off Chip Driver Impedance Adjustment supported• Read Data Strobe supported (x8 only)ORDERING INFORMATION* X means speed gradePart No. Configuration PackageHY5PS12423(L)F-X* 128Mx460 BallFBGAHY5PS12823(L)F-X* 64Mx8HY5PS121623(L)F -X* 32Mx1684Ball FBGAOPERATING FREQUENCY Grade tCK(ns) CL tRCD tRP Unit-D435 333Clk-D445 444Clk-D54 3.75 4 4 4 Clk-D55 3.75 5 5 5 ClkRev. 0.52/Nov. 02 4 HY5PS12423(L)F HY5PS12823(L)FHY5PS121623(L)F128Mx4 DDR-II PIN CONFIGURATION3VSSDMVDDQDQ3VSSWEBA1A1A5A9NC2NCVSSQDQ1VSSQVREFCKEBA0A10A3A7A121VDDNCVDDQNCVDDLBA2,NCVSSVDDABCDEFGHJKL7VSSQDQSVDDQDQ2VSSDLRASCASA2A6A11NC8DQSVSSQDQ0VSSQCKCKCSA0A4A8A139VDDQNCVDDQNCVDDODTVDDVSSROW AND COLUMN ADDRESS TABLEITEMS 128Mx4Organization 32M x 4 x 4banksRow Address A0 - A13Column Address A0-A9, A11Bank Address BA0, BA1Auto Precharge Flag A10Refresh 8KRev. 0.52/Nov. 02 5 HY5PS12423(L)F HY5PS12823(L)FHY5PS121623(L)F64Mx8 DDR-II PIN CONFIGURATIONROW AND COLUMN ADDRESS TABLEITEMS 64Mx8Organization 16M x 8 x 4banksRow Address A0 - A13Column Address A0-A9Bank Address BA0, BA1Auto Precharge Flag A10Refresh 8K3VSSDM, RDQSVDDQDQ3VSSWEBA1A1A5A9NC2NU, RDQSVSSQDQ1VSSQVREFCKEBA0A10A3A7A121VDDDQ6VDDQDQ4VDDLBA2,NCVSSVDDABCDEFGHJKL7VSSQDQSVDDQDQ2VSSDLRASCASA2A6A11NC8DQSVSSQDQ0VSSQCKCKCSA0A4A8A139VDDQDQ7VDDQDQ5VDDODTVDDVSSRev. 0.52/Nov. 02 6 HY5PS12423(L)F HY5PS12823(L)FHY5PS121623(L)F32Mx16 DDR-II PIN CONFIGURATION3VSSUDMVDDQDQ11VSSWEBA1A1A5A9NC2NCVSSQDQ9VSSQVREFCKEBA0A10A3A7A121VDDDQ14VDDQDQ12VDDLBA2,NCVSSVDDABCDEFGHJKL7VSSQUDQSVDDQDQ10VSSDLRASCASA2A6A11NC8UDQSVSSQDQ8VSSQCKCKCSA0A4A8A139VDDQDQ15VDDQDQ13VDDODTVDDVSSVSSLDMVDDQDQ3NCVSSQDQ1VSSQVDDDQ6VDDQDQ4ABCDVSSQLDQSVDDQDQ2LDQSVSSQDQ0VSSQVDDQDQ7VDDQDQ5ROW AND COLUMN ADDRESS TABLEITEMS 64Mx8Organization 8M x 16 x 4banksRow Address A0 - A12Column Address A0-A9Bank Address BA0, BA1Auto Precharge Flag A10Refresh 8KRev. 0.52/Nov. 02 7 HY5PS12423(L)F HY5PS12823(L)FHY5PS121623(L)FPIN DESCRIPTIONPIN TYPE DESCRIPTIONCK, CKInputClock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).CKE InputClock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are dis-abled during SELF REFRESH. CKE is an SSTL_18 input, but will detect an LVCMOS LOW level after Vdd is applied. CSInputChip Select : Enables or disables all inputs except CK, CK, CKE, DQS and DM. All com-mands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. BA0, BA1 InputBank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-CHARGE command is being applied.A0 ~ A13 InputAddress Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.ODT InputOn Die Termination Control : ODT enables on die termination resistance internal to the DDR II SDRAM. When enabled, on die termination is only applied to DQ, DQS, DQS, RDQS, RDQS, and DM.DM, RDQSNC, RDQS(LDM, UDM)InputInput Data Mask : DM is an input mask signal for write data. Input Data is masked when DM


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