Direct RDRAM™ 256/288-Mbit (1Mx16/18x16d)OverviewFeaturesFigure 1: Direct RDRAM CSP PackageKey Timing Parameters/Part NumbersRelated DocumentationPinouts and DefinitionsCenter-Bonded Devices - PreliminaryTable 1: Center Bonded Device (top view)Table 2: Pin DescriptionFigure 2: 256/288-Mbit (1Mx16/18x16d) Direct RDRAM...General DescriptionPacket FormatTable 3: Field Description for ROWA Packet and ROW...Table 4: Field Description for COLC Packet, COLM P...Figure 3: Packet FormatsField Encoding SummaryTable 5: Device Field Encodings for ROWA Packet an...Table 6: ROWA Packet and ROWR Packet Field Encodin...Table 7: COLC Packet Field EncodingsTable 8: COLM Packet and COLX Packet Field Encodin...DQ Packet TimingFigure 4: Read (Q) and Write (D) Data Packet - Tim...COLM Packet to D Packet MappingFigure 5: Mapping Between COLM Packet and D Packet...ROW-to-ROW Packet InteractionFigure 6: ROW-to-ROW Packet Interaction- TimingTable 9: ROW-to-ROW Packet Interaction - RulesROW-to-ROW Interaction - continuedROW-to-COL Packet InteractionFigure 7: ROW-to-COL Packet Interaction- TimingTable 10: ROW-to-COL Packet Interaction - RulesCOL-to-COL Packet InteractionFigure 8: COL-to-COL Packet Interaction- TimingTable 11: COL-to-COL Packet Interaction - RulesCOL-to-ROW Packet InteractionFigure 9: COL-to-ROW Packet Interaction- TimingTable 12: COL-to-ROW Packet Interaction - RulesROW-to-ROW ExamplesFigure 10: Row Packet ExampleFigure 11: Row Packet ExampleFigure 12: Row Packet ExamplesRow and Column Cycle DescriptionPrecharge MechanismsFigure 13: Precharge via PRER Command in ROWR Pack...Figure 14: Offsets for Alternate Precharge Mechani...Read Transaction - ExampleFigure 15: Read Transaction ExampleWrite Transaction - ExampleFigure 16: Write Transaction ExampleWrite/Retire - ExamplesFigure 17: Normal Retire (left) and Retire/Read Or...Write/Retire Examples - continuedFigure 18: Retire Held Off by Read (left) and Cont...Figure 19: Retire Held Off by Reads to Same Device...Interleaved Write - ExampleFigure 20: Interleaved Write Transaction with Two ...Interleaved Read - ExampleInterleaved RRWW - ExampleFigure 21: Interleaved Read Transaction with Two D...Figure 22: Interleaved RRWW Sequence with Two Dual...Control Register TransactionsFigure 23: Serial Write (SWR) Transaction to Contr...Figure 24: Serial Read (SRD) Transaction Control R...Control Register PacketsFigure 25: SETR, CLRR,SETF TransactionTable 13: Control Register Packet FormatsTable 14: Field Description for Control Register P...InitializationFigure 26: SIO Reset SequenceControl Register SummaryTable 15: Control Register SummaryFigure 27: INIT RegisterFigure 28: CNFGA RegisterFigure 29: CNFGB RegisterFigure 30: TEST RegisterFigure 31: DEVID RegisterFigure 32: REFB RegisterFigure 33: CCA RegisterFigure 34: REFR RegisterFigure 35: CCB RegisterFigure 36: NAPX RegisterFigure 37: PDNXA RegisterFigure 38: PDNX RegisterFigure 39: TPARM RegisterFigure 40: TFRM RegisterFigure 41: TCDLY1 RegisterFigure 42: SKIP RegisterFigure 43: TEST RegistersFigure 44: TCYCLE RegisterPower State ManagementTable 16: Power State SummaryFigure 45: Power State Transition DiagramFigure 46: STBY Entry (left) and STBY Exit (right)...Figure 47: NAP Entry (left) and PDN Entry (right)Figure 48: NAP and PDN ExitFigure 49: NAP Entry/Exit Windows (left) and PDN E...RefreshRefresh (continued)Figure 50: REFA/REFP Refresh Transaction ExampleFigure 51: NAP/PDN Exit - tBURST RequirementCurrent and Temperature ControlFigure 52: Current Control CAL/SAM Transaction Exa...Figure 53: Temperature Calibration (TCEN-TCAL) Tra...Timing ConditionsTable 17: Timing ConditionsTable 18: Electrical ConditionsTiming CharacteristicsTable 19: Timing CharacteristicsElectrical CharacteristicsTable 20: Electrical CharacteristicsRSL - ClockingFigure 54: RSL Timing - Clock SignalsRSL - Receive TimingFigure 55: RSL Timing - Data Signals for ReceiveRSL - Transmit TimingFigure 56: RSL Timing - Data Signals for TransmitCMOS - Receive TimingFigure 57: CMOS Timing - Data Signals for ReceiveFigure 58: CMOS Timing - Device Address for NAP or...CMOS - Transmit TimingFigure 59: CMOS Timing - Data Signals for Transmit...RSL - Domain Crossing WindowFigure 60: RSL Transmit - Crossing Read DomainsTiming ParametersTable 21: Timing Parameter SummaryAbsolute Maximum RatingsTable 22: Absolute Maximum RatingsIDD - Supply Current ProfileTable 23: Supply Current ProfileTable 24: Supply Current at InitializationCapacitance and InductanceFigure 61: Equivalent Load Circuit for RSL PinsTable 25: RSL Pin ParasiticsTable 26: CMOS Pin ParasiticsCenter-Bonded uBGA Package (16x6)Figure 62: Center-Bonded uBGA PackageTable 27: Center-Bonded uBGA Package DimensionsPinouts and Definitions (9x8 OPTIONAL)Center-Bonded Devices - PreliminaryTable 28: 9x8 OPTIONAL Center-Bonded Device (top v...Table 29: 9x8 OPTIONAL Center-Bonded Device (top v...Center-Bonded uBGA Package (9x8 OPTIONAL)Figure 63: Center-Bonded uBGA PackageTable 30: Center-Bonded uBGA Package DimensionsInterleaved Device ModeFigure 64: ACT, PRE, RD, and WR Commands for Eight...Figure 65: Mapping from DEVID2..0 and DC2..0 Field...Figure 66: Mapping from DEVID2..0 and DC2..0 Field...Table Of ContentsRAMBUSDocument DL0105 Version 1.1 Preliminary Information Page 1OverviewThe Rambus Direct RDRAM™ is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 256/288-Mbit Direct Rambus DRAMs (RDRAM) are extremely high-speed CMOS DRAMs organized as 16M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz to 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simulta-neous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's 16 banks support up to four simulta-neous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. The two data bits in the x18 organization are general and can be used for addi-tional storage and bandwidth or for error
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