Heading - Memory System OrganizationHeading - DRAM System OrganizationBody - Where is the data?Heading - Rank Part 1Body - It’s a “bank” of chips that responds to a single command and returns data.Body - “Bank” terminology already used.Heading - Rank Part 2Heading - BankHeading - Row and Column RevisitedBody - “Column” DefinedHeading - Channel Part 1Heading - Channel Part 2Heading - Address Mapping IHeading - Address Mapping IIBody - Heading - Address Mapping IIIBody - Heading - Where’s the data? Part 1Heading - Where’s the data? Part 2Heading - Where’s the data? Part 3Heading - Memory Modules IHeading - Memory Modules IIHeading - Memory Modules IIIHeading - SPD: Serial Presence DetectHeading - SDRAM Chip: 54 Pin TSOPHeading - Kingston SDRAM DIMMDRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandMemory System OrganizationSingleChannelSDRAMControllerDimm1 Dimm2Dimm3 Dimm4Data BusAddr & Cmd Chip (DIMM) Select“Mesh Topology”DRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandDRAM System OrganizationWhere is the data?CPURequest (Read)(Physical Address)(Cachline length = 64B)MagicMemory ControllerDataCommandSequenceRow address = ?Column Address ?Rank Address = ?Bank Address = ?DataRow?Rank?Bank?Column?DRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandRank Part 1It’s a “bank” of chips that responds to a single command and returns data.“Bank” terminology already used.MagicMemory ControllerBankRankDRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandRank Part 2Single Sided DimmOne RankDouble Sided DimmTwo RanksRambus RIMMRank Count isNumber of DevicesSDRAMSDRAMSDRAM/DDR SDRAM system: 4~6 ranksRDRAM system: <= 32 ranksDRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandRow, Bitlines and WordlinesBank SDRAM/DDR SDRAM system: 4 banks RDRAM system: “32” split or 16 full banks“Banks” of indepedent memory arraysinside of a DRAM ChipBank 0 Array(8196 x 512 x 16)Sense AmpBank 0 Array(8196 x 512 x 16)Sense AmpBank 0 Array(8196 x 512 x 16)Sense AmpBank 0 Array(8196 x 512 x 16)Sense AmpBank 3Bank 2Bank 1Control LogicI/O GatingDRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandRow and Column Revisited“Column” Defined“One Row” of DRAMColumn: Smallest addressable quantity of DRAM on chipSDRAM*: column size == chip data bus width (4, 8,16, 32)RDRAM: column size != chip data bus width (128 bit fixed)4 bit wide columnsSDRAM*: get “n” columns per access. n = (1, 2, 4, 8)RDRAM: get 1 column per access. #2 #3 #4 #5#0 #1DRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandChannel Part 1MemoryControllerDRDRAMDRDRAMMemoryControllerDDR SDRAMMemoryControllerDDR SDRAMDDR SDRAMCurrent “PC Class” memory system.1 physical channel of DDR SDRAMIntel i850 DRDRAM memory system.2 physical channel. 1 logical channelIntel “Granite Bay” memory system.2 physical channel. 1 logical channelDRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)Channel Part 2MemoryControllerDRDRAMDRDRAMAlpha EV7 DRDRAM memory system8* physical channels. 2 logical channelsMemoryControllerDRDRAMDRDRAMDRDRAMDRDRAMDRDRAMDRDRAMDRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)Address Mapping ICPUMagicMemory ControllerPhysicalAddressMemoryAddressVariable numbers ofrank, coumn, row.DRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)Address Mapping IIDevice config 64 Meg x 4 32 Meg x 8 16 Meg x 16Configuration 16 M x 4 x 4 bks 8 M x 8 x 4 bks 4 M x 16 x 4 bksrow addressing 8K (A0 - A12) 8K (A0 - A12) 8K (A0 - A12)bank addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)col addressing 2K(A0-A9,A11) 1K (A0-A9) 512 (A0- A8)8 of the x8 devicesform 64 bit wide data bus4 of the x16 devicesform 64 bit wide data bus“DRAM page size” differs with different configurations.DRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)Address Mapping IIIDevice config 16 Meg x 16Configuration 4 M x 16 x 4 bksrow addressing 8K (A0 - A12)bank addressing 4 (BA0, BA1)col addressing 512 (A0- A8)02311121314262827293132 bit physical address (byte addressable)nomemoryrankidbankidcolumnidrowidnotusedOne Address Mapping Scheme for 512 MB of MemoryDRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)Where’s the data? Part 1Read RequestMagicMemory ControllerPhysical Address: 0x0AC75C3802311121314262827293132 bit physical address (byte addressable)nomemoryrankidbankidcolumnidrowidnotusedRank id = 1Bank id = 1Row id = 0x0B1DColumn id = 0x187DRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)Where’s the data? Part 2Rank id = 1Bank id = 1Row id = 0x0B1DColumn id = 0x187FPM / EDO / SDRAM / etc.DRAM MemorySystem: Lecture 3Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page