130nm Flash+Logic: Technology and ApplicationsOutlineOutline“Wireless Internet on a Chip”Wireless Integration VisionTechnologies for IntegrationIntegration: Power-Performance ImprovementsOutlineKey Challenges for Integration:OutlineMultiple Gate OxidesLow Thermal BudgetTrench Isolation & SalicideHigh Density/ High Performance: 110nm Poly Gate for Logic Performance6 Layer Metal for Logic DensityWireless Internet on a Chip –Enabled by Silicon IntegrationCost Effective IntegrationKey Attributes for Integration: ETOX® Flash Meets All CriteriaOutlineIntel® PXA800F Cellular ProcessorIntel® PXA800F Cellular ProcessorPerformance HeadroomIntel® PXA800F Cellular ProcessorSpace SavingsFull GSM/GPRS System SolutionLeadership By IntegrationConclusions1R130nm Flash+Logic: Technology and ApplicationsAl FazioIntel CorporationWireless Internet on a Chip –Enabled by Silicon Integration2ROutlinez Motivation for Flash + Logic Integrationz Technology Challengesz Meeting The Challengesz Product Applicationsz Conclusions3ROutlinezzMotivation for Flash + Logic IntegrationMotivation for Flash + Logic Integrationz Technology Challengesz Meeting The Challengesz Product Applicationsz Conclusions4R“Wireless Internet on a Chip”Vision : Cellular Silicon Function Integration for Cost, Performance, Power, and SizeMajor “Silicon” Components of a Cellular SystemFlash MemorySRAM MemoryBaseband LogicDigital Signal ProcessorApplications ProcessorPeripheralsDigital/AnalogRadio TransmitRadio ReceiveRadio Power AmpRadio PassivesPower SuppliesRF/AnalogIntel® Micro Signal ArchitectureCellular Protocol LogicBaseband ProcessorIntel® FlashPeripheralsIntel® XScale™RXTXAnalogMixed SignalRFTransceiverKeypad369258147#0*LCDDisplayIntel® XScale™ Processor High End/PDA’s DataHigh End/PDA’s DataInternal SRAMRF Front End RF Front End SolutionsSolutionsAdditional Intel® Flash & SRAM as NeededPowerManagementWhat is the Optimal Integration Strategy?5RNon-Volatile Flash MemoryDense Volatile MemoryFlash SRAM Digital Wireless Integration VisionDigital CMOSDigitalAnalog CMOS Analog Powerg)Factors Determining Function Partitioning :• Technology Capability & Cost Optimization• Board Space (I/O) & Cost Minimization• Power/Performance Optimization• Noise IsolationNVM,DVM Digital Dig- Tx NVM,DVM Digital, Dig-TxAFE (AnaloPower ManagementSingle Pkg2G/2.5G Cell PhoneAnalog Power RadioRF Rx, TxRF Rx, Tx, PassivesPassivesPassivesAFE(RF)Single Chip 2G/2.5G Cell PhoneMEMSPA, MEMS Radio PAPAFutureFutureTodayTodayTomorrowTomorrow6RTechnologies for IntegrationFirst Steps –Integrate Digital and Memory SubsystemsNon-Volatile Flash MemoryFlash SRAM Digital Intel® Micro Signal DSPDigitalIntel® XScale™ µPPeripheralsVolatile SRAMMemoryValues :• High Performance of Wide Internal Bus• Low Power/Noise with No External Bus• Small Form Factor with Fewer I/O’sSynergies :•Moore’s Law Scaling (2x/2yr)• Synergistic Si Technologies• Mature, Volume Technologies7RIntegration: Power-Performance ImprovementsIncreasing Battery LifeIntegrated FlashInternal Priority Code FlashExternal Embedded Memory CardMemorySDRAMMemory<1V Core<1v I/O1.8v Core1v I/O1.8v Core1.8-1.5v I/O3v Core3v I/O3v > 1.8v Core1.8v I/OCardEmbedded MemoryStacked, Internal Bus FlashPackageProcessorFlash010203040506070Lower Memory Latencies through Integration100MHz SDRAMIntegratedFlashIntegrated SRAMPower mWIntel Proc w/ Int FlashOthersIntel Gen Apps Integrated OnlyInternal vs.. External Memory Power Consumption 2(CPUs normalized to 312 MHz)80/20 int/ext mem splitClock CyclesIncreasing Performance8ROutlinez Motivation for Flash + Logic IntegrationzzTechnology ChallengesTechnology Challengesz Meeting The Challengesz Product Applicationsz Conclusions9RKey Challenges for Integration:z Small & Identical memory cell size integrated vs. discrete– Same cell size: Integration (SOC) & Stacking (SIP) Complementaryz Multiple Gate Oxides– Advanced Logic Gates, Advanced Memory Gates & Support Gates z Low Thermal Budget– Advanced Logic Transistorsz Trench Isolation & Salicide Integration– Small SRAM cell size, Advanced Logic Transistorsz Multi-Layer Metal– High Gate Densityz Cost Effective Integration– Minimize flash or logic unique high cost process steps10ROutlinez Motivation for Flash + Logic Integrationz Technology ChallengeszzMeeting The ChallengesMeeting The Challengesz Product Applicationsz Conclusions11RSmall & Identical memory cell size integrated vs. discrete0.16µ2Flash“Manitoba”12RMultiple Gate Oxides2.4nmNAHigh Performance Logic7nm7nmI/O15nm15nmHigh Voltage9nm9nmTunnel OxideIntegrated FlashDiscrete FlashOne Additional Gate Oxide: Evolution of base Flash Process13RLow Thermal BudgetzFlash Cell formed prior to Logic GatezBasic Process Flow:Flash Tunnel OxideFlash Floating Gate PolyFlash ONOFlash High Voltage OxideI/O OxideLogic OxideFlash and Logic Gate PatterningS/D ImplantsStandard Flash FlowFlash+Logic FlowStandard Logic Flow14RTrench Isolation & SalicideDrainSourceSpacerPoly-1Poly-2SalicideSpacer15RHigh Density/ High Performance: 110nm Poly Gate for Logic PerformanceSRAM Cell16R6 Layer Metal for Logic DensityM1M2M3M5M6M4M2M1M3M4M66 Metal Stack Al Metal & W plug Via6 Metal Architecture, Low K Dielectric17RWireless Internet on a Chip –Enabled by Silicon Integration2.5µ2SRAM“Manitoba”6 Layers DenseInterconnect6 Metal Stack Al Metal & W plug Via6 Metal Architecture, Low K Dielectric 0.16µ2Flash110nmState of the Art : Flash + SRAM + Logic= Leadership Integration= High Performance + Low Power + Small Size110nm GatePerformanceTransistor18RCost Effective Integrationz Only 1 critical mask required over logic (flash gate)– Lab feasibility demonstrating ability to share with logic gatez Other steps are shared (isolation, contact…), non-critical layers (implants…), or self-aligned1X60 80 100 120 140(mm^2)19RKey Attributes for Integration:ETOX® Flash Meets All Criteriaz Small & Identical cell size integrated vs. discrete– Flash: <10λ2cell size, <5λ2with MLC– Same cell size: Integration (SOC) & Stacking (SIP) Complementaryz Multiple Gate Oxides– Discrete Flash processing includes multiple gates z Low Thermal Budget– Flash cell processing precedes logic gate formation z Trench Isolation & Salicide Integration– Discrete Flash integrates trench & salicide since 0.25µ nodez Multi-Layer Metal– Flash & Logic fully compatiblez Cost Effective Integration– Only 1