ContentsRevision History1.0 Introduction1.1 Nomenclature1.2 Acronyms1.3 Conventions2.0 Device Description2.1 Product Overview2.2 Ballout Diagrams for VF BGA PackageFigure 1. 7x8 Active-Ball Matrix for 64-, and 128-Mbit Densities in VF BGA PackagesFigure 2. 7x9 Active-Ball Matrix for 256-Mbit Density in VF BGA Package2.3 Ballout Diagrams for Intel® Stacked Chip Scale PackageFigure 3. 88-Ball (80-Active Ball) Stacked-CSP Package Ballout2.4 Signal Descriptions for VF BGA PackageTable 1. Signal Descriptions2.4.1 Signal Descriptions for 128/0 and 256/0 Stacked-CSPTable 2. Device Signal Descriptions for S-CSP (Sheet 1 of 2)2.5 Memory MapTable 3. Top Parameter Memory MapTable 4. Bottom Parameter Memory Map3.0 Device Operations3.1 Bus Operations3.1.1 Reads3.1.2 Writes3.1.3 Output Disable3.1.4 Standby3.1.5 Reset3.2 Device CommandsTable 5. Command Bus Cycles3.3 Command DefinitionsTable 6. Command Codes and Definitions (Sheet 1 of 2)4.0 Read Operations4.1 Asynchronous Page-Mode Read4.2 Synchronous Burst-Mode Read4.2.1 Burst Suspend4.3 Read Configuration Register (RCR)Table 7. Read Configuration Register Description4.3.1 Read Mode4.3.2 Latency CountFigure 4. First-Access Latency CountTable 8. LC and Frequency Support for Bin 1 tAVQV/tCHQV (85ns / 14ns)Table 9. LC and Frequency Support for Bin 2 tAVQV/tCHQV (95ns / 17ns)Table 10. LC and Frequency Support for Bin 1 tAVQV/tCHQV (90ns / 17ns)Table 11. LC and Frequency Support for Bin 2 tAVQV/tCHQV (110ns / 20ns)Figure 5. Example Latency Count Setting4.3.3 WAIT Polarity4.3.3.1 WAIT Signal FunctionTable 12. WAIT Summary Table4.3.4 Data HoldFigure 6. Data Hold Timing4.3.5 WAIT Delay4.3.6 Burst SequenceTable 13. Burst Sequence Word Ordering (Sheet 1 of 2)4.3.7 Clock Edge4.3.8 Burst Wrap4.3.9 Burst Length5.0 Programming Operations5.1 Word Programming5.1.1 Factory Word Programming5.2 Buffered Programming5.3 Buffered Enhanced Factory Programming5.3.1 Buffered EFP Requirements and Considerations5.3.2 Buffered EFP Setup Phase5.3.3 Buffered EFP Program/Verify Phase5.3.4 Buffered EFP Exit Phase5.4 Program Suspend5.5 Program Resume5.6 Program ProtectionFigure 7. Example VPP Supply Connections6.0 Erase Operations6.1 Block Erase6.2 Erase Suspend6.3 Erase Resume6.4 Erase Protection7.0 Security Modes7.1 Block Locking7.1.1 Lock Block7.1.2 Unlock Block7.1.3 Lock-Down Block7.1.4 Block Lock StatusFigure 8. Block Locking State Diagram7.1.5 Block Locking During Suspend7.2 Protection RegistersFigure 9. Protection Register Map7.2.1 Reading the Protection Registers7.2.2 Programming the Protection Registers7.2.3 Locking the Protection Registers8.0 Dual-Operation Considerations8.1 Memory Partitioning8.2 Read-While-Write Command SequencesFigure 10. Operating Mode with Correct Command Sequence ExampleFigure 11. Operating Mode with Correct Command Sequence ExampleFigure 12. Operating Mode with Illegal Command Sequence Example8.2.1 Simultaneous Operation Details8.2.2 Synchronous and Asynchronous Read-While-Write Characteristics and Waveforms8.2.2.1 Write operation to asynchronous read transition8.2.2.2 Synchronous read to write operation transition8.2.3 Read Operation During Buffered Programming Flowchart8.3 Simultaneous Operation RestrictionsTable 14. Simultaneous Operation Restrictions9.0 Special Read States9.1 Read Status RegisterTable 15. Status Register Description (Sheet 1 of 2)9.1.1 Clear Status Register9.2 Read Device IdentifierTable 16. Device Identifier InformationTable 17. Device ID codes9.3 CFI Query10.0 Power and Reset10.1 Power-Up/Down Characteristics10.2 Power Supply Decoupling10.3 Automatic Power Saving (APS)10.4 Reset Characteristics11.0 Thermal and DC Characteristics11.1 Absolute Maximum Ratings11.2 Operating Conditions11.3 DC Current Characteristics11.4 DC Voltage Characteristics12.0 AC Characteristics12.1 AC Read Specifications (VCCQ = 1.35 V - 2.0 V)12.2 AC Read Specifications (VCCQ = 1.7 V - 2.0 V)Figure 13. Asynchronous Single-Word Read with ADV# LowFigure 14. Asynchronous Single-Word Read with ADV# LatchFigure 15. Asynchronous Page-Mode Read TimingFigure 16. Synchronous Single-Word Array or Non-array Read TimingFigure 17. Continuous Burst Read, showing an Output Delay TimingFigure 18. Synchronous Burst-Mode Four-Word Read TimingFigure 19. Burst Suspend Timing12.3 AC Write SpecificationsFigure 20. Write to Write TimingFigure 21. Asynchronous Read to Write TimingFigure 22. Write to Asynchronous Read TimingFigure 23. Synchronous Read to Write TimingFigure 24. Write to Synchronous Read Timing12.4 Program and Erase Characteristics12.5 Reset SpecificationsFigure 25. Reset Operation Waveforms12.6 AC Test ConditionsFigure 26. AC Input/Output Reference WaveformFigure 27. Transient Equivalent Testing Load CircuitTable 18. Test configuration component value for worst case speed conditionsFigure 28. Clock Input AC Waveform12.7 CapacitanceTable 19. CapacitanceAppendix A Write State Machine (WSM)Figure 29. Write State Machine - Next State Table (Sheet 1 of 6)Figure 29. Write State Machine - Next State Table (Sheet 2 of 6)Figure 29. Write State Machine - Next State Table (Sheet 3 of 6)Figure 29. Write State Machine - Next State Table (Sheet 4 of 6)Figure 29. Write State Machine - Next State Table (Sheet 5 of 6)Figure 29. Write State Machine - Next State Table (Sheet 6 of 6)Appendix B FlowchartsFigure 30. Word Program FlowchartFigure 31. Program Suspend/Resume FlowchartFigure 32. Buffer Program FlowchartFigure 33. Buffered EFP FlowchartFigure 34. Block Erase FlowchartFigure 35. Erase Suspend/Resume FlowchartFigure 36. Block Lock Operations FlowchartFigure 37. Protection Register Programming FlowchartFigure 38. Read While Buffered Programming FlowchartAppendix C Common Flash InterfaceTable 20. Summary of Query Structure Output as a Function of Device and ModeTable 21. Example of Query Structure Output of x16- DevicesTable 22. Query StructureTable 23. CFI IdentificationTable 24. System Interface InformationTable 25. Device Geometry DefinitionTable 26. Primary Vendor-Specific Extended QueryTable 27. Protection Register InformationTable 28. Burst Read InformationTable 29. Partition and Erase-block Region InformationAppendix D Mechanical InformationFigure 39. 64- and 128-Mbit; 56-Ball VF BGA Package Drawing and DimensionsFigure 40. 256-Mbit; 79-Ball VF BGA Package Drawing and DimensionsFigure 41. Mechanical Specification for the 128-Mbit device in an 88-ball (80-active ball) Intel® Stacked Chip Scale Package Drawing and DimensionsFigure 42. Mechanical Specification for