Introductions• Overview• Memory System Architecture• DRAM Architecture and Circuits• DRAM Memory System Terminology and IssuesCost - Benefit CriterionMemory System DesignMemory Request OverviewBasicsDRAM ORGANIZATIONBasicsBUS TRANSMISSIONBasics[PRECHARGE and] ROW ACCESSBasicsCOLUMN ACCESSBasicsDATA TRANSFERnote: page mode enables overlap with CASBasicsBUS TRANSMISSIONBasicsDRAM Interfaces: ProtocolThe Digital FantasyDRAM Interface: SignalsInterface:Signal PropagationInterface: Clocking IssuesClocking IssuesPath Length DifferentialTiming VariationsLoading BalanceTopologySDRAM Topology ExampleRDRAM Topology ExampleI/O TechnologyI/O - Differential PairI/O - Multi Level LogicPackagingAccess ProtocolAccess Protocol (r/r)Access Protocol (r/w)Technology Roadmap (ITRS)Choices for FutureResearch Areas: TopologyUnidirectional Topology:• Write Packets sent on Command Bus• Pins used for Command/Address/Data• Further Increase of Logic on DRAM chipsMemory Commands?Address MappingAccess Distribution for Temp Control Avoid Bank Conflicts Access Reordering for performanceExample: Bank ConflictsExample: Access ReorderingDRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandIntroductions• Overview • Memory System Architecture• DRAM Architecture and Circuits• DRAM Memory System Terminology and IssuesDRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandCost - Benefit CriterionLogic OverheadPower ConsumptionPackage CostTest andDRAMSystemDesignBandwidthLatencyImplementationInterconnectCostDRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandNow we’ll really get our hands dirty, and try to become DRAM designers. That is, we want to understand the tradeoffs, and design our own memory system with DRAM cells. By doing this, we can gain some insight into some of the basis of claims by proponents of various DRAM memory systems.A Memory System is a system that has many parts. It’s a set of technologies and design decisions. All of the parts are inter-related, but for the sake of discussion, we’ll splite the components into ovals seen here, and try to examine each part of a DRAM system separately.Memory System DesignDRAMMemory SystemTopologyI/O TechnologyAccess ProtocolDRAM ChipArchitectureClock NetworkRow BufferAddress MappingManagementPin CountChip PackagingDRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandProfessor Jacob has shown yoou some nice timing diagrams, I too will show you some nice timing diagrams, but the timing diagrams are a simplification that hides the details of implemetation. Why don’t they just run the system at XXX MHz like the other guy? Then the latency would be much better, and the bandwidth would be extreme. Perhaps they can’t, and we’ll explain why. To understand the reason why some systems can operate at XXX MHz while others cannot, we must go digging past the nice timing digrams and the architectural block diagrams and see what turns up underneath. So underneath the timing diagram, we find this....Memory Request OverviewFetchDecodeWBMemExecvirtual to physical address translation(DTLB access) [A1][A2] L1 D-Cacheaccess. If missthen proceed to[A3] L2 Cacheaccess. If missthen send to BIUBus Interface Unit (BIU)obtains data from mainmemory [A4 + B][B1] BIU arbitrates [B2] requestsent to system controller[B8] system controller returns data to CPUStages of instruction executionProceeding throughthe memory hierarchyin a modern processor[B3]physical addr. to memory addr.translation. [B4] memory L1cacheL2cacheDTLBProcessor CoreBIU (Bus Interface Unit)RAMfor ownership ofaddress bus ** [B5] memoryaddr. Setup requestscheduling**(RAS/CAS)[A1][B8][A4][A2][A3]** Steps not required for some processor/system controllers. protocol dependant.[B4][B3][B2][B1]I/O to memory trafficmemory request schedulingphysical to memory addrmapping[B7][B5]readdatabuffersystem controllerprocessorDRAM core[B6][B6, B7] DRAM dev.obtains data and returns to controller Part A: Searchingon-chip for dataPart B: Goingoff-chip for data Progression of a Memory Read Transaction Request Through Memory SystemDRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandBasicsDRAM ORGANIZATION... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMStorage elementSwitching elementBit LineWord LineData In/OutBuffersSense AmpsColumn Decoder(capacitor)DRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandso how do you interact with this thing? let’s look at a traditional organization first ... CPU connects to a memory controller that connects to the DRAM itself.let’s look at a read operationBasicsBUS TRANSMISSIONBUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderDRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandat this point, all but lines are attt the 1/2 voltage level. the read discharges the capacitors onto the bit lines ... this pulls the lines just a little bit high or a little bit low; the sense amps detect the change and recover the full signalthe read is destructive -- the capacitors have been discharged ... however, when the sense amps pull the lines to the full logic-level (either high or low), the transistors are kept open and so allow their attached capacitors to become recharged(if they hold a ‘1’ value)Basics[PRECHARGE and] ROW ACCESS AKA: OPEN a DRAM Page/RowRAS (Row Address Strobe)ororACT (Activate a DRAM Page/Row)BUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderDRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandonce the data is valid on ALL of the bit lines, you can select a subset of the bits and send them to the output buffers ... CAS picks one of the bitsbig point: cannot do another RAS or precharge of the lines until finished reading the column data ... can’t change the values on the bit lines or the output of the sense amps until it has been read by the memory controllerBasicsCOLUMN ACCESS READ CommandorCAS: Column Address StrobeBUSMEMORYCONTROLLERCPU... Bit Lines...MemoryArrayRow Decoder. .. Word Lines ...DRAMData In/OutBuffersSense AmpsColumn DecoderDRAM MemorySystem: Lecture 1Spring 2003Bruce JacobDavid WangUniversity ofMarylandthen the data is valid on the data bus ... depending on what you are