Welcome To The RDF Consumer TrackInterfaces: More than Just SiliconTI DLP : Before & AfterConsumer: Sony PS2 = SimplicityToday’s Consumer Track AgendaYellowstone:A Next Generation Memory Signaling Technology3D Games, PC Graphics, Networking Driving Memory PerformanceYellowstone OverviewWhat Makes Yellowstone Different?Yellowstone: A Quantum Leap in Memory Signaling TechnologyYellowstone FeaturesFlexPhase Technology In ActionYellowstone:Physical Layer OverviewDRSL: Differential RSLUltra Low Voltage SignalingODR: Octal Data RateLow Cost SignalingIntroducing FlexPhaseTM TechnologyFlexPhase Technology Close-upFlexPhase Simplifies Chip-to-chip InterfacesExample Yellowstone FlexPhase ImplementationYellowstone Memory System Layout ExampleAdditional Performance Optimizations25-50 GB/s Yellowstone Memory System Example3.2GHz Yellowstone Demo System3.2GHz Test Chip Data Eye DiagramYellowstone SummaryDifferential System DesignOutlineIntroduction to Differential SignalingAdvantages of differential signalingComparison of signaling voltage levelsFundamentals of Transmission LinesDerivation of a transmission line equationsTransmission line equationsCharacteristic parameters of coupled linesDifferential- and common-mode parameters of a differential pairL and C of lossless differential linesCommon- and differential-mode networksDesign of Differential Transmission LinesDifferential system using conventional PCB and packaging technologiesModeling of Differential Transmission LinesScattering parametersMixed-mode scattering parametersTransmission line parameter extractionExamples of Differential LinesComparisons of characteristic parametersDifferential impedancesCommon-mode responsesConclusionsYellowstone Channel Design And ModelingAgendaAgendaSignaling TechnologyYellowstone SignalingAgendaChannel Design ChallengesChannel Modeling/Simulation ChallengesAgendaHow to ensure robust system under the worst case conditions?Physical Layer Design ParametersChannel Design MethodologySystem InterconnectSystem Interconnect ModelChannel Modeling MethodologyWhy Perform Both Frequency And Time Domain Analysis?AgendaPackage/PCB Design and ModelingPCB Transmission Line DesignBroadside Coupled Stripline ZoDifferential ImpedanceCommon-mode ResponseExample of CSP Package Cross SectionCSP Package ModelingCSP Package ModelWirebond PackageA Signal Net In A PBGA PackagePackage Characterization ProceduresThe Cross Section Of The PBGA PackagePackage Design OptionsFullwave AnalysisTransfer Functions For Designs With The Plating StubsResonant Frequencies For Design I and IITransfer Functions For Designs Without The Plating StubsEffects Of Plating Stub At 3.2GbpsAgendaPCB Trace Model CorrelationPCB Trace Model Correlation (cont’d)PCB Trace Impedance CorrelationPackage Model Correlation In Frequency Domain Without Model TuningPackage Model Correlation in Frequency Domain with Model TuningCharacterization BoardFrequency Domain CorrelationPCB and Connector Prototype BoardCorrelation with VNACorrelation With TDR/TDTCorrelation With Scope at 3.2GbpsEye Diagram Correlation At 3.2GbpsMeasured System Eye Diagram With PRBS Data PatternSilicon Evaluation BoardCorrelation With TDRCorrelation With ScopeCorrelation With Scope at 3.2Gbps3.2Gbps System Board Set-upWaveform Correlation at Driver With 3.2Gbps Data RateWaveform Correlation at Receiver With 3.2Gbps Data RateMeasured System Eye Diagram at 3.2GbpsChannel Design MethodologyConclusionsRambus and High-Speed Test SolutionsRambus’ Role In TestHistory of Rambus’ High Speed TestingNeed for High Speed TestersGuest SpeakersTesting High-Speed Interfaces on Agilent 93000 SOC SeriesContentFull Coverage from IP Qualification to ProductionApplication ExampleTest List for High-Speed InterfacesImpedance TestAt Speed Receiver Test: Sensitivity TestAt Speed Receiver Test: Skew InsertionClock-Data Output SkewDynamic Voltage TestVoltage Separation: Vswing, VcomRise/Fall Time Measurements: SetupEye Diagram: SetupMeasurement Results: SerDes Device with Data Pattern (DDJ + RJ)The Source Synchronous Test ChallengeSummaryTesting Next Generation Bus TechnologiesOutlineThe Need for Bus SpeedI/O TrendsI/O TrendsSource Synchronous InterfacesSource Sync Test ChallengeSource Sync Test ChallengeSource Sync Test ChallengeSource Sync Test SolutionSource Sync Test SolutionHigh Speed Serial InterfacesHigh Speed Serial Test ChallengeHigh Speed Serial Test SolutionHigh Speed Serial SolutionHigh Speed Serial Test SolutionHigh Speed Serial Test SolutionConclusionsWelcome To The RDF Consumer TrackRich WarmkeMarketing ManagerMemory Interface DivisionRambus Inc.October 29th, 2002Interfaces: More than Just SiliconSignal Integrity &System EngineeringValidation &Production TestPCBDesignSystemComponentsCost ReductionStrategiesPackageDesignCircuitDesignYellowstoneWorld’s fastest chip to chip solutionsDLP™ Products using RDRAMSharp NotevisionM25XSharp NotevisionM20XHP xp21HP sb31LG D44WDLP-AL1Samsung HLM437WSamsung SP43L2HXAnd many more to be announced…TI DLP : Before & AfterWith RDRAMWithout RDRAMFour SDRAM devices vs. OneRDRAMConsumer: Sony PS2 = Simplicity Integrated memory controller Ultra-small form factor Low component count EE + RDRAM = 2.3in2Granularity & Low Pincount = Highest Performance & Lowest SYSTEM CostToday’s Consumer Track Agenda 10AM: Yellowstone Technology Overview 11AM: Differential System Design 11:30AM: Yellowstone System Design & Modeling 12:30PM: Lunch 1:30PM: High-Speed Test Solutions Andreas Olenyi – Agilent Steve Lomaro - NPTest 2:30PM: Small Form-factor Designs Using RDRAMYellowstone:A Next Generation Memory Signaling Technology3D Games, PC Graphics, Networking Driving Memory PerformanceBandwidth requirementsapproaching30 GB/secBandwidth Bandwidth requirementsrequirementsapproachingapproaching30 GB/sec30 GB/secYellowstone Overview Next generation memory signaling technology for graphics, consumer, and networking applications High performance and low cost 3.2GHz data rate with roadmap to 6.4GHz Enables 10 to 100GB/s memory system bandwidthDefined by listening to customer requirementsWhat Makes Yellowstone Different? World’s fastest DRAM signaling Enables first differential DRAM Simple memory system design Enables lower cost than specialty DRAMsYellowstone: A Quantum Leap in Memory Signaling TechnologyYellowstoneRDRAMYellowstone Features DRSL: Ultra low voltage differential signaling for low power ODR: