Heading - Alternative Memories: Non- Volatile Memories: FlashHeading - What is DRAM?Bullet - • (Relatively) fast reads and (relatively) fast writesBullet - • Unlimited number of writesBullet - • Volatile - loses data storage without powerBullet - • Dynamic - loses data without periodic refreshBullet - • Could be fabricated using similar materials and (relatively) similar silicon based pro...Heading - Advantage/disadvantage of Alternatives:Bullet - • (Relatively) slower reads and (on some) really slow writesBullet - • (Some) limited number of writesBullet - • Non-Volatile - keeps data storage without powerBullet - • May require new materials and (relatively) different process technologies as leading e...Heading - Flash:Basic Idea IHeading - Charge PumpHeading - Flash:Basic Idea IIHeading - GranularityHeading - NAND Flash ArrayHeading - NOR Flash ArrayHeading - NAND versus NORHeading - Multi (voltage) Level CellHeading - Reads and WritesHeading - RedundancyHeading - Comparison to DRAMDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 1Alternative Memories: Non-Volatile Memories: FlashGateFloating GateSourceDrainSingle Transistor Flash Memory CellDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 2What is DRAM?• (Relatively) fast reads and (relatively) fast writes• Unlimited number of writes• Volatile - loses data storage without power• Dynamic - loses data without periodic refresh• Could be fabricated using similar materials and (relatively) similar silicon based process technologies as leading edge processorsDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 3Advantage/disadvantage of Alternatives:• (Relatively) slower reads and (on some) really slow writes• (Some) limited number of writes• Non-Volatile - keeps data storage without power• May require new materials and (relatively) different process technologies as leading edge processorsDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 4Flash:Basic Idea IControl GateFloating GateSourceDrainTunnel Oxide- Electrical charges are forced to tunnel through oxides and trapped in the floating gate. - Trapped chages in floating gate then alters Vt- High voltage forces tunneling- Limited number of write cyclesWord LineBit Line- Differences in Vt of transistor then sensed as 0/1DRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 5Charge Pump- Build up larger voltage for programming floating gateVddGNDVoutCLKCLKVout = ( Vdd - Vt ) x N + VddIdealized charge pumping circuit“N” is the number of stagesDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 6Flash:Basic Idea IIControl GateFloating GateSourceDrainTunnel Oxide- Explicit program and erase cyclesWord LineBit LineProgramEraseDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 7GranularityWrite/Erase entire deviceBlock write/eraseBit by bit write/erase(Flash devices)DRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 8NAND Flash ArrayBit LineBit Line SelectBit Line SelectSource LineWord LineWord LineWord LineWord LineCDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 9NOR Flash ArraySource LineBit LineWord LineWord LineWord LineWord LineDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 10NAND versus NORSmaller Cell SizeNOR NANDBetter E/W EnduranceFast Read (~100ns)Slow Write (~10 us)Slow Read (~1 us)“Fast” Write (~1 us)Used for Code Used for Data(>100K vs >10K) (~40%)DRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 11Multi (voltage) Level CellControl GateFloating GateSourceDrainTunnel OxideWord LineBit LineProgramEraselogic 01 rangelogic 00 rangevoltagelogic 10 rangelogic 11 rangeVref_2Vref_0Vref_1DRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 12Reads and Writes- Reads are relatively straight forward- Writes are complex- Did the cells erase properly?- How long do we hold the reverse biascurrents to “erase”?- Did the write succeed?- If the write failed, recover, remap andre-write to another sector/blockDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 13RedundancySense Amps512 columns16 spareMuxDRAM MemorySystem: Lecture 14Spring 2003Bruce JacobDavid WangUniversity ofMarylandslide 14Comparison to DRAM- Row/column/sense amp structure and- Controller logic/sequence has to be access sequence is similarmuch more sophisticated- Multiple banks per chip so “simultaneous”R/W can be