CHAPTER The Single Cycle Datapath So far we have been dealing with the internal design of building blocks that will form the foundations of various computer architectures These building blocks will be aggregated in various ways to produce computer architectures with distinct cost performance characteristics Consider the analogy of constructing buildings At the lowest level we have common components various types of rooms foundations walls and stairwells integrated with plumbing wiring and temperature control devices Each component comes in various sizes and shapes and constructed with different materials From these basic components we can produce buildings with widely varying sizes costs and capacities Computer architecture can be thought of in a similar manner By using multiplexors ALUs memories and register files we can construct a datapath and interconnect them with point to point signals and shared buses We refer to such an organization as a datapath for the obvious reason it captures the flow of data between components that operate on and store data We can produce architectures of widely varying costs and performance Embedded controllers that operate in automobiles must be compact reliable and cheap whereas supercomputers can cost millions of dollars might be a bit more finicky consume vastly more power but deliver the performance necessary for computationally intensive problems such as weather modeling drug design and crash test simulations This is the essence of engineering designing and constructing systems that meet specifications for performance and reliability at a specific cost To make appropriate trade offs we must have an accurate understanding of the cost and performance of various implementation options Advances in technology allow us to continually push the capability of computer architectures and thereby enable powerful supercomputers of 20 years ago to reside on our desktop at a fraction of the cost Can you think of any other industry segment that has produced such relentless increases in performance at continually reducing cost levels Architecture Digital Logic Control 1 The Single Cycle Datapath In this chapter we begin with the idea that design of computer architectures can be viewed as the aggregation of combinational and sequential components that we have discussed to date into larger computers that you will recognize on the desktop in your video games and in your portable devices However simply aggregating components is not very meaningful unless we can orchestrate their interaction to do something useful In this sense we start with the idea that designing an architecture is about control Getting multiple large components to collectively do something useful can be viewed as a problem of control We start with an elementary datapath and construct its control This datapath is incrementally built to a modern CPU wherein we design and understand the operation of the controller since we already understand the individual components in isolation Then we can see how it is possible to generate a whole range of architectures by simply aggregating distinct components to satisfy a particular price performance design point and designing the controller for such a datapath We start with a simple single cycle datapath The Single Cycle Datapath The simplest datapath is the single cycle datapath The basic components are a register file to store the data and functional units to operate on the data such as an adder subtractor logical unit and a barrel shifter We have constructed all of these components from basic gates and switches and should be familiar with their operation The issue now is how can we compose larger systems with these components How large should the data be How many bits In our example we will pick 32 bits a number that is compatible with datapaths found in the majority of modern microprocessors controllers and signal processing chips One of the components is a register file that has 32 registers where each register is 32 bits wide In addition we will assume that this register file has two read ports and one write port The block diagram is shown Figure 1 and includes the rwe register write enable control signal for enabling write operations to the register file This register file can produce the values of the contents of two registers on its output ports Addresses must be provide the two registers being read With 32 registers we need 5 bits to specify the address of a register Therefore we need 10 bits to specify the address of the two read registers In addition if we are to write a register with a value we need another 5 bits to identify the register that is to receive this value and 32 bits for the value that is to be written into this register Register 0 is special and will always contain the value 0 In the examples at the conclusion of the chapter it will become evident that this is a useful feature Additional functional units are shown in Figure 1 The control signals for the functional units include signals for the adder subtractor shift unit and the logic unit The adder subtractor requires one bit to specify the operation and one bit to enable it to drive the output bus The shifter is simi 2 Single Cycle Datapath The Single Cycle Datapath X 5 Y Z 5 5 Value 1 Register lf lu en File rwe Data 32 32 32 32 32 Logical Unit Value 2 32 32 32 32 32 st add sub Shifter au en shift en 32 32 FIGURE 1 Single cycle datapath components larly constructed one input provides the data to be shifted and a second input provides the amount by which the data is to be shifted as a two s complement number Positive numbers refer to a shift right by that amount and negative numbers refer to a shift left by that amount In addition a two bit shift type field specifies whether this is a logical shift 00 arithmetic shift 01 or a rotate 10 operation Finally the logical unit requires four bits as input to specify any boolean function on two bits For example to perform the exclusive OR operation the input pattern would be 0110 This function is applied to each pair of bits of the input operands These basic architectural components are aggregated into a datapath as shown in Figure 2 Each functional unit has two inputs that are provided by the register file Each output of the register file is connected to a bus These two buses X and Y serve to carry input values to the functional units The outputs of the functional units drive a third bus the Z bus that is used to carry the data value to