Slide 1CMOS InverterCMOS Voltage Transfer CharacteristicsPull-Up and Pull-Down NetworkPUN/PDN of a CMOS InverterGate Symbol of a CMOS InverterPUN/PDN of a NAND GateSlide 8NAND Gate SymbolPUN/PDN of a NOR GateSlide 11NOR Gate SymbolHow about an AND gateAn OR GateWhat’s the Function of the following CMOS Network?Yet Another XOR CMOS NetworkExclusive-OR (XOR) GateHow about XNOR GateSlide 19A Systematic Method (I) Start from Pull-Up NetworkA Systematic Method (II) Start from Pull-Down NetworkSystematic ApproachesExample 1 (Method I)Slide 24Slide 25Slide 26Slide 27Slide 28Drawing the Schematic using Method IIAn Alternative for XNOR Gate (Method I)Example 3Slide 32Slide 33Slide 34Example 4Another ExampleECE2030 Introduction to Computer EngineeringLecture 4: CMOS NetworkProf. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech22CMOS Inverter•Connect the following terminals of a PMOS and an NMOS–Gates–DrainsVinVoutVddGndVoutVinVinVin = HIGHVout = LOW (Gnd)ONONOFFOFFVddGndVoutVinVinVin = LOWVout = HIGH (Vdd)ONONOFFOFFVddPMOSGroundNMOS33CMOS Voltage Transfer CharacteristicsVddGndVinVoutPMOSNMOSOFF: V_GateToSource < V_ThresholdLINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSourceNote that in the CMOS Inverter V_GateToSource = V_in44Pull-Up and Pull-Down Network•CMOS network consists of a Pull-UP Network (PUN) and a Pull-Down Network (PDN)•PUN consists of a set of PMOS transistors•PDN consists of a set of NMOS transistors•PUN and PDN implementations are complimentary to each other–PMOS NOMS–Series topology Parallel topology….I0I1In-1OUPTUTVddPUNGndPDN55PUN/PDN of a CMOS InverterA B0 11 ZA B0 Z1 0A B0 11 0Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkVddAGndBCMOS Inverter66Gate Symbol of a CMOS InverterVddAGndBCMOS InverterA BB = Ā77PUN/PDN of a NAND GateA B C0 0 10 1 11 0 11 1 ZA B C0 0 Z0 1 Z1 0 Z1 1 0Pull-UpNetworkPull-DownNetworkVddABABC88PUN/PDN of a NAND GateA B C0 0 10 1 11 0 11 1 ZA B C0 0 Z0 1 Z1 0 Z1 1 0A B C0 0 10 1 11 0 11 1 0Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkVddABABC99NAND Gate SymbolA B C0 0 10 1 11 0 11 1 0VddABABCABCTruth TableBAC 1010PUN/PDN of a NOR GateA B C0 0 10 1 Z1 0 Z1 1 ZA B C0 0 Z0 1 01 0 01 1 0Pull-UpNetworkPull-DownNetworkVddACBAB1111PUN/PDN of a NOR GateA B C0 0 10 1 Z1 0 Z1 1 ZA B C0 0 Z0 1 01 0 01 1 0A B C0 0 10 1 01 0 01 1 0Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkACBABVdd1212NOR Gate SymbolA B C0 0 10 1 01 0 01 1 0ABCTruth TableACBABBAC Vdd1313How about an AND gateVddABAVddGndCNANDInverterBC = A BABC1414An OR GateABABVddVddGndCInverterNORABCBAC 1515What’s the Function of the following CMOS Network?A B C0 0 Z0 1 11 0 11 1 ZA B C0 0 00 1 Z1 0 Z1 1 0A B C0 0 00 1 11 0 11 1 0Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkFunction = XORXORVddABAAABBBC1616Yet Another XOR CMOS NetworkVddABAAABBBCA B C0 0 Z0 1 11 0 11 1 ZA B C0 0 00 1 Z1 0 Z1 1 0A B C0 0 00 1 11 0 11 1 0Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkFunction = XORXOR1717Exclusive-OR (XOR) GateVddABAAABBBCA B C0 0 00 1 11 0 11 1 0ABCTruth TableBABABAC 1818How about XNORXNOR GateA B C0 0 10 1 01 0 01 1 1ABCTruth TableBABABAC How do we draw thecorresponding CMOS networkgiven a Boolean equation?1919How about XNORXNOR GateA B C0 0 10 1 01 0 01 1 1ABCTruth TableBABAC VddABAAABBBCVddXORInverter2020A Systematic Method (I)Start from Pull-Up Network•Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN•Draw PUNPUN using PMOS based on the Boolean eqn–ANDAND operation drawn in seriesseries–OROR operation drawn in parallelparallel•Invert each variablevariable of the Boolean eqn as the gate input for each PMOS in the PUN•Draw PDNPDN using NMOS in complementary form–Parallel (PUN) to series (PDN)–Series (PUN) to parallel (PDN)•Label with the same inputs of PUN•Label the output2121A Systematic Method (II)Start from Pull-Down Network•Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN•Invert the Boolean eqn •With the Right-Hand Side of the newly inverted equation, Draw PDNPDN using NMOS–ANDAND operation drawn in seriesseries–OROR operation drawn in parallelparallel•Label each variablevariable of the Boolean eqn as the gate input for each NMOS in the PDN•Draw PUNPUN using PMOS in complementary form–Parallel (PUN) to series (PDN)–Series (PUN) to parallel (PDN)•Label with the same inputs of PUN•Label the output2222Systematic Approaches•Note that both methods lead to exactly the same implementation of a CMOS network•The reason to invert Output equation in (II) is because–Output (F) is conducting to “ground”, i.e. 0, when there is a path formed by input NMOS transistors–Inversion will force the desired result from the equation•Example–F=Ā·C + B: When (A=0 and C=1) or B=1, F=1. However, in the PDN (NMOS) of a CMOS network, F=0, i.e. an inverse result. –Revisit how a NAND CMOS network is implemented•Inverting each PMOS input in (I) follow the same reasoning2323Example 1 (Method I)BCAF In seriesIn parallelVdd(1) Draw the Pull-Up Network2424Example 1 (Method I)BCAF In seriesIn parallelVdd(2) Assign the complemented inputACB2525Example 1 (Method I)BCAF In seriesIn parallelVdd(3) Draw the Pull-Down Network in the complementary formACBAC2626Example 1 (Method I)BCAF In seriesIn parallelVdd(3) Draw the Pull-Down Network in the complementary formACBACB2727Example 1 (Method I)BCAF In seriesIn parallelVddLabel the output FACBACBF2828Example 1 (Method I)BCAF In seriesIn parallelVddACBACBFA B C F0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1Truth Table2929Drawing the Schematic using Method IIBCAF BC)A(FBCA FBCAFVddACBACBFThis is exactly the same CMOS network with the schematic by Method I3030An Alternative for XNOR Gate (Method I)A B C0 0 10 1 01 0 01 1 1ABCTruth TableBABAC VddABABAABBC3131Example 3)C(ABDAF Start from the innermost termABDACAD3232Example 3)C(ABDAF Start from the innermost termABDACADAC3333Example 3)C(ABDAF Start from the innermost termABDACADACB3434Example
View Full Document
Unlocking...