R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-1MEMORY SYSTEMS•CHAPTER XCHAPTER XMEMORY SYSTEMSREAD MEMORY NOTES ON COURSE WEBPAGECONSIDER READING PAGES 285-310 FROM MANO AND KIMEOTHER USEFUL RAM MATERIAL AT ARS TECHNICAR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-2MEMORY SYSTEMSINTRODUCTIONMEMORY SYSTEMS•MEMORY SYSTEMS-INTRODUCTION•A number of different types of memories and programmable logic devices exist.• Random-access memory (RAM)• Read-only memory (ROM)• Programmable logic devices (PLDs)• Programmable logic arrays (PLAs)• Programmable array logic (PAL)• Programmable gate arrays (PGAs)• Programmable sequential arrays (PSAs)• Field-programmable gate arrays (FPGAs)•Due to time limitations, we will only cover RAM.Two-level combinationalnetworksMulti-levelcombinationalTw o - l eve land sequentialnetworksMemoriesR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-3MEMORY SYSTEMSTYPES OF RAMMEMORY SYSTEMS•MEMORY SYSTEMS-INTRODUCTION•Two main categories of random-access memory (RAM) exist.• Static memory or static RAM (SRAM)• Information bits are latched such as with a latch or a flip-flop.• Typical SRAM implementations require 4 to 6 transistors.• Dynamic memory or dynamic RAM (DRAM)• Information bits are stored in the form of electric charges on capacitors.• The capacitors will discharge over time.• Refreshing the memory cell is required before the capacitor has discharged to much of the electric charge.• Most DRAM implementations use 1 transistor and 1 capacitor.R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-4STATIC RAMSRAM CELLS (1)MEMORY SYSTEMS•MEMORY SYSTEMS-INTRODUCTION-TYPES OF RAM•An inefficient SRAM bit cell can be formed as follows.•How many transistors required for this design?• 2*4 for inverters + 2*2 for TGs = 12 transistors.• Very expensive in terms of silicon real estate!!!Select (word line)DDTGTGR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-5STATIC RAMSRAM CELLS (2)MEMORY SYSTEMS•MEMORY SYSTEMS•STATIC RAM-SRAM CELLS•The structure for a 6 transistor implementation of an SRAM 1-bit cell is as follows. (We will refer to this as the “6T” design)• The select, or word line, chooses the bit cell when high.• When selected, the new / is latched into the feedback loop.Select (word line)DD6T designDDR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-6STATIC RAMSRAM CELLS (3)MEMORY SYSTEMS•MEMORY SYSTEMS•STATIC RAM-SRAM CELLS•Of course, the previous SRAM cell structure can be drawn as follows, replacing each inverter with 2 transistors.Select (word line)DD6T designVDDR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-7STATIC RAMSRAM CELLS (4)MEMORY SYSTEMS•MEMORY SYSTEMS•STATIC RAM-SRAM CELLS•A 4 transistor design for an SRAM bit cell is as follows.• Notice replacement of pMOS transistors with load resistors.• This is for your own information. We won’t be testing on the 4T design.Select (word line)DD4T designVDDR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-8DYNAMIC RAMDRAM CELLS (1)MEMORY SYSTEMS•MEMORY SYSTEMS•STATIC RAM-SRAM CELLS•A dynamic RAM cell stores the bit as a charge in a capacitor.•This bit must be refreshed periodically (>100s of times a second).•How many transistors required for this design?• 2*1 for TG and 2*1 for inverter = 4 transistors.• Still expensive considering the extra refresh circuitry required!Select (word line)DTGTransmission gate openswhen selected to chargeor discharge capacitor.This charge stores the bit.R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-9DYNAMIC RAMDRAM CELLS (2)MEMORY SYSTEMS•MEMORY SYSTEMS•STATIC RAM•DYNAMIC RAM-DRAM CELLS•The capacitor charging structure can be simplified as follows.•This structure for a DRAM bit cell is what is used in practice in real implementations.• Very little chip real estate is used!!!Select (word line)Transmission gate openswhen selected to chargeor discharge capacitor.This charge stores the bit.D1T designR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-10MEMORY UNITSSPECIFICATIONMEMORY SYSTEMS•MEMORY SYSTEMS•STATIC RAM•DYNAMIC RAM-DRAM CELLS•Having developed bit cells, either SRAM or DRAM bit cells, they can now be pieced together forming a memory unit.•What do we want to specify in the design of a memory unit?• The number of bits.• This gives the total number of bits that the memory unit can store.• The grouping of bits into words.• Accessing 1 bit at a time might be inconvenient, so, grouping bits into words is often done.• Common examples of word bit sizes are 4, 8, 16, 32, and 64.• The number of words in the memory unit (addressable words).• This is a function of the word size and total number of bits.R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-11MEMORY UNITSDESCRIPTIONMEMORY SYSTEMS•STATIC RAM•DYNAMIC RAM•MEMORY UNITS-SPECIFICATION•In describing the capacity of a memory unit, the following is used• # addresses x word size• Example: 1Mx8•If a memory unit is described as 1Mx8, then it has• addresses,•8 bits per word at each address location,•8 data lines for the 8 bit words,•20 address lines to specify the addresses,• and bits in the entire memory unit.1M 2201048576==1M 2201048576==1048576()8()8388608=R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-12MEMORY UNITSDESCRIPTION EXAMPLESMEMORY SYSTEMS•DYNAMIC RAM•MEMORY UNITS-SPECIFICATION-DESCRIPTION•Some further examples of memory descriptions are given below.• Note that the last four columns are all described with the information in the first column.• Try to fill in the empy cells for the last two rows.Memory Total bits # of addresses # address lines # data lines1Mx8 8388608 1048576 20 81Kx4 4096 1024 10 42Mx4 8388608 2097152 21 44Mx1 4194304 4194304 22 12Mx32 67108864 2097152 21 3216Kx648Mx8R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-13MEMORY UNITSBLOCK DIAGRAM (1)MEMORY SYSTEMS•MEMORY UNITS-SPECIFICATION-DESCRIPTION-DESCRIPTION EXAMPLES•Below is a general block diagram for a memory unit.• The k address lines access a word in the memory for input or output.• To simplify drawing, we now form buses of n (or k) lines.Memory unit2k wordsn bits per wordReadWritek address linesn data output linesn data input lineskWRR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER X-14MEMORY UNITSBLOCK DIAGRAM (2)MEMORY SYSTEMS•MEMORY UNITS-DESCRIPTION-DESCRIPTION EXAMPLES-BLOCK DIAGRAM•To conserve pins, the following layout is more
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