ECE2030 Introduction to Computer Engineering Lecture 1: OverviewECE2030 SyllabusECE2030 SyllabusObjective: Digital Design PrincipleSlide 5Hierarchy of ComputationSlide 7Slide 8Zoom-in a System ComponentSlide 10Slide 11Slide 12Slide 13A Generic Intel-based PC SystemDual-Core Itanium 2 (Montecito)Integrated Circuit ComplexityMinimum Feature SizeAverage Transistor Price per yearProcessor Market SegmentationAnalog Signal vs. DigitalBinary SignalsVoltage Range of Binary SignalsECE2030 Introduction to Computer EngineeringLecture 1: OverviewProf. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech22•Instructor: Prof. Hsien-Hsin “Sean” Lee•Email: [email protected]•Course web: http://www.ece.gatech.edu/~leehs/ECE2030•My office: Klaus 2318•Teaching Materials: –Morris Mano and Charles Kime, “Logic and Computer Design Fundamentals,” the 4th edition–Course notes and handouts (check out course web)–TA: to be announced later•Attending classes is important !!ECE2030 Syllabus33ECE2030 Syllabus •Grading policy–3 Homework assignment: 5% each–1 Programming assignment: 10%–3 in-class exams: 15% each –1 final exam: 30%–[100,90]=A; (90,80]=B; (80,70]=C,(70,55]=D,(55,0]=F–Will scale…•All homework: turn-in in the first 5 minutes “in class” of the due day•All exams: closed books, closed notes, no calculator•Honor code •Use T-Square (http://tsquare.gatech.edu) for your homework and exam grades44Objective: Digital Design Principle•Number systems•Boolean algebra•Switch and CMOS design •Combinational logic–Logic gates–Building blocks: de/mux, de/encoder, shifters, adder/subtractor, multiplier–Logic minimization–Mixed logic•Sequential logic–Latches, Flip-flops–Counters–State machines: Mealy/Moore machines55Objective: Digital Design Principle•Memory and Programmable Devices–Register, RAM, ROM, PLA, PAL •Architectural concept–Instruction set architecture (ISA)–Stored-Program Computer and Sequential Control (von Neumann architecture)–Datapath–Branches•Processor and Software Convention–MIPS ISA–Procedural calls: Stack66Hierarchy of ComputationProblemProblemProblemProblemAlgorithAlgorithmsmsAlgorithAlgorithmsmsProgramming inProgramming inHigh-Level LanguageHigh-Level LanguageProgramming inProgramming inHigh-Level LanguageHigh-Level LanguageCompiler/Assembler/Compiler/Assembler/LinkerLinkerCompiler/Assembler/Compiler/Assembler/LinkerLinkerInstruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)BinaryBinaryBinaryBinarySystem architectureSystem architectureSystem architectureSystem architectureTarget Machine Target Machine (one implementation)(one implementation)Target Machine Target Machine (one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architectureFunctional units/Functional units/Building blocksBuilding blocksFunctional units/Functional units/Building blocksBuilding blocksGates Level Gates Level Design Design Gates Level Gates Level Design Design TransistorsTransistorsTransistorsTransistorsManufacturingManufacturingManufacturingManufacturing77Hierarchy of ComputationProblemProblemProblemProblemAlgorithAlgorithmsmsAlgorithAlgorithmsmsProgramming inProgramming inHigh-Level LanguageHigh-Level LanguageProgramming inProgramming inHigh-Level LanguageHigh-Level LanguageCompiler/Assembler/Compiler/Assembler/LinkerLinkerCompiler/Assembler/Compiler/Assembler/LinkerLinkerInstruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)BinaryBinaryBinaryBinarySystem architectureSystem architectureSystem architectureSystem architectureTarget Machine Target Machine (one implementation)(one implementation)Target Machine Target Machine (one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architectureFunctional units/Functional units/Building blocksBuilding blocksFunctional units/Functional units/Building blocksBuilding blocksGates Level Gates Level Design Design Gates Level Gates Level Design Design TransistorsTransistorsTransistorsTransistorsManufacturingManufacturingManufacturingManufacturingSystem LevelSystem LevelSystem LevelSystem LevelHuman LevelHuman LevelHuman LevelHuman LevelRTL Level RTL Level RTL Level RTL Level Logic Level Logic Level Logic Level Logic Level Circuit Level Circuit Level Circuit Level Circuit Level Silicon Level Silicon Level Silicon Level Silicon Level88Our Focus in 2030Hierarchy of ComputationProblemProblemProblemProblemAlgorithAlgorithmsmsAlgorithAlgorithmsmsProgramming inProgramming inHigh-Level LanguageHigh-Level LanguageProgramming inProgramming inHigh-Level LanguageHigh-Level LanguageCompiler/Assembler/Compiler/Assembler/LinkerLinkerCompiler/Assembler/Compiler/Assembler/LinkerLinkerInstruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)BinaryBinaryBinaryBinarySystem architectureSystem architectureSystem architectureSystem architectureTarget Machine Target Machine (one implementation)(one implementation)Target Machine Target Machine (one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architectureFunctional units/Functional units/Building blocksBuilding blocksFunctional units/Functional units/Building blocksBuilding blocksGates Level Gates Level Design Design Gates Level Gates Level Design Design TransistorsTransistorsTransistorsTransistorsManufacturingManufacturingManufacturingManufacturingSystem LevelSystem LevelSystem LevelSystem LevelHuman LevelHuman LevelHuman LevelHuman LevelRTL Level RTL Level RTL Level RTL Level Logic Level Logic Level Logic Level Logic Level Circuit Level Circuit Level Circuit Level Circuit Level Silicon Level Silicon Level Silicon Level Silicon Level99Zoom-in a System Component1010John BardeenWilliam ShockleyWalter BrattainCirca. 1947, Bell LabsNobel Prize in Physics 1956GDSSwitch1111Inventors of Integrated CircuitsRobert NoyceJack KilbyNobel Prize in Physics 2000“The Tyranny of Numbers” Challenge1212Fairchild Traitorous 8Gordon E. Moore circa. 19651313Moore’s LawExponential growthExponential growthTransistor count will be doubled every
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