R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-1DATAPATH ELEMENTS•CHAPTER XICHAPTER XIDATAPATH ELEMENTSREAD DATAPATH ELEMENTS FREE-DOC ON COURSE WEBPAGER.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-2DATAPATH ELEMENTSINTRODUCTIONDATAPATH ELEMENTS•DATAPATH ELEMENTS-INTRODUCTION•So far we have discussed many small components and building blocks.•One final step in our building blocks before we can start to piece together a microprocessor is various datapath elements.• We have already discussed portions of these datapath elements in terms of other components and building blocks.• We will now consider some of these components and building blocks in ways that will make the design of a microprocessor a little easier in the next chapter.R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-3REGISTER FILESREGISTER LAYOUTDATAPATH ELEMENTS•DATAPATH ELEMENTS-INTRODUCTION•A general register file with registers that are each -bits wide is illustrated below.• The and signals indicate which register to read/write, respectively.mn×mnRegister 0Register 1Register m -1DataOutDataInnnw0w1wm 1–r1rm1–r0rkwjR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-4REGISTER FILESWRITE DECODERDATAPATH ELEMENTS•DATAPATH ELEMENTS•REGISTER FILES-REGISTER LAYOUT•For writing to a register, we include a write address with decoder.• A given Write Address (with Write Enable = 1) selects which register, 0 through m - 1, to store the input from Data In.Register 0Register 1Register m -1DataOutDataInnnw0w1wm 1–Decoder01m-1WriteAddressWriteEnabler1rm1–r0R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-5REGISTER FILESREAD DECODERDATAPATH ELEMENTS•DATAPATH ELEMENTS•REGISTER FILES-REGISTER LAYOUT-WRITE DECODER•For reading from a register, we include a read address with decoder.• A given Read Address (with Read Enable = 1) selects which register, 0 through m - 1, to read from and output to Data Out.• Could have multiple data outputs with multiple read address decoders.Register 0Register 1Register m -1DataOutDataInnnw0w1wm 1–r0r1rm 1–Decoder01m-1ReadAddressReadEnableR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-6REGISTER FILES32-BIT WORD, 32 REGISTERSDATAPATH ELEMENTS•REGISTER FILES-REGISTER LAYOUT-WRITE DECODER-READ DECODER•For the upcoming datapath designs in the next chapter, we want to have a 32x32 register file with one write input and two read outputs.• Note: Two data outputs implemented with two read address decoders.ZdiXdoYdoZwaXraYraZdi - Z data inXdo - X data outYdo - Y data outZwa - Z write addressXra - X read addressYra - Y read address32323232x32registerfile5 5 5rwerwe - register write enableClkR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-7ADDER/SUBTRACTORGENERAL UNIT DIAGRAMDATAPATH ELEMENTS•REGISTER FILES-WRITE DECODER-READ DECODER-32X32 REGISTER FILE•An n-bit adder/subtractor unit is often illustrated as follows.• This unit would have n full-adders internally.adder/subtratorunitABFnnnas⁄enableSelect eitheraddition (0)or subtraction (1)Enable unit (1)or disable unit (0)R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-8ADDER/SUBTRACTOROTHER UNIT SIGNALSDATAPATH ELEMENTS•REGISTER FILES•ADDER/SUBTRACTOR-GENERAL UNIT DIAGRAM•Other signals often included with an adder/subtractor are shown below.ABFnnnas⁄enableCinCarry-inor Borrow-inCarry-outor Borrow-outCoutFlags- Overflow- Negative (F<0?)- Zero (F=0?)R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-9LOGICAL UNITINTRODUCTIONDATAPATH ELEMENTS•REGISTER FILES•ADDER/SUBTRACTOR-GENERAL UNIT DIAGRAM-OTHER UNIT SIGNALS•A useful unit would be one that can take two n-bit inputs and perform some logical operation between each of the bits to get an n-bit output.• For example, given the 8-bit values 0001 1110 and 1001 1000, we might want to find the bit-wise logical OR.• Or similarly, the bit-wise logical AND of the two 8-bit values.• These types of operations are often used for masking and setting bits.0001 11101001 10001001 1110bit-wiselogical OR0001 11101001 10000001 1000bit-wiselogical ANDR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-10LOGICAL UNITGENERAL UNIT DIAGRAMDATAPATH ELEMENTS•REGISTER FILES•ADDER/SUBTRACTOR•LOGICAL UNIT-INTRODUCTION•Below is a general unit diagram for an n-bit logical unit.• Logical operations, such as AND/OR/NOT/NAND/NOR/etc., are done for each bit of and to form .logicalunitABFnnnLFenable4Enable unit (1)or disable unit (0)Logical Function (LF)on 2 bitsAB FR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-11LOGICAL UNIT4-BIT LOGICAL FUNCTIONS (LF)DATAPATH ELEMENTS•ADDER/SUBTRACTOR•LOGICAL UNIT-INTRODUCTION-GENERAL UNIT DIAGRAM•Recall the possible logic functions for two bits, and .• We can use the column Fn as the 4-bit LF input for the logical unit.000000000011111111010000111100001111100011001100110011110101010101010101ABABF0F1F2F3F4F5F6F7F8F9F10F11F12F13F14F1501AB A B+AB⊕ABAB+AB BAAB⊕Null IdentityInhibitionImplicationR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-12LOGICAL UNITBIT SLICE IMPLEMENTATIONDATAPATH ELEMENTS•LOGICAL UNIT-INTRODUCTION-GENERAL UNIT DIAGRAM-4-BIT LOGICAL FUNCTIONS•A number of internal implementations exist for the logical unit.• The easiest is to use a 4-to-1 multiplexer for each bit as follows4X1MULTIPLEXERS1S00123FABLF0LF1LF2LF3EModule EnableNote: When you look ata design for each bit,it is known as abit sliceRequire n of theseto form our n-bitlogical unit.Take Fn columnfrom previousslide as LF inputR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-13LOGICAL UNITBIT SLICE IMPLEMENTATIONDATAPATH ELEMENTS•LOGICAL UNIT-GENERAL UNIT DIAGRAM-4-BIT LOGICAL FUNCTIONS-BIT SLICE IMPLEMENTAT.•The following are example LF inputs for a logical unit bit slice.4X1MULTIPLEXERS1S00123FAB0111EModule EnableORfunction4X1MULTIPLEXERS1S00123FAB1110EModule EnableNANDfunctionABAB+R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XI-14SHIFT UNITINTRODUCTIONDATAPATH ELEMENTS•LOGICAL UNIT-GENERAL UNIT DIAGRAM-4-BIT LOGICAL FUNCTIONS-BIT SLICE IMPLEMENTAT.•We have already discussed the bulk about shift units in previous chapters.•As given in the Free-Doc, there are different types of shift units.• Logical shift• Arithmetic shift• Circular shift (this is just a rotate unit)•We want to discuss an implementation, the barrel shifter, that will be useful in our single cycle datapath computer we will design next chapter.R.M. Dansereau; v.1.0INTRO. TO COMP.
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