Slide 1Basic ShiftingLogical ShiftArithmetic ShiftExamples of Arithmetic Shift4-bit Logical Shifter4-bit Logical Shifter using 4-to-1 Mux4-bit Arithmetic Shifter w/ 4-to-1 MuxSlide 9Slide 10RotatorBarrel ShifterBarrel Shifter Design w/ Mux (D3)Barrel Shifter Design Alternative (16-bit)Barrel Shifter Design w/ nMOSFETSlide 16Slide 17Unsigned Binary MultiplyUnsigned Integer Multiplier (2-bit)Unsigned Integer Multiplier (3-bit)4-bit Unsigned Integer MultiplierPropagation DelayCarry-Save MultiplierPropagation Delay of Carry-Save MultiplierSigned Binary MultiplySlide 26Slide 27More Examples (1)More Examples (2)More Examples (3)ECE2030 Introduction to Computer EngineeringLecture 13: Building Blocks for Combinational Logic (4) Shifters, MultipliersProf. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech2Basic Shifting•Shift directions–Left (multiply by 2)–Right (divide by 2)•Take floor value if the result is not an integer•Floor value of XX (or X) is the greatest integer number less than or equal to X, X, E.g.5/2 = 2-3/2 = -2•Shift types–Logical (or unsigned) –Arithmetic (or signed)3Logical Shift•Shift Left–MSB: Shifted out–LSB: Shifted in with a “0”–Examples: •(11001011 << 1) = 10010110•(11001011 << 3) = 01011000•Shift right–MSB: Shifted in with a “0”–LSB: Shifted out–Examples: (Some ISA use triple “>” for logical right shift)•(11001011 >>> 1) = 01100101•(11001011 >>> 3) = 000110014Arithmetic Shift•Shift left–MSB: Shifted out, however, be aware of overflow/underflow –LSB: Shifted in with a “0”–Examples:•(1100 << 1) = 1000•(1100 << 3) = 0000 (Incorrect!) Underflow•Shift right–MSB: Retain “sign bit” –LSB: Shifted out –Examples:•(1100 >> 1) = 1110 (Retain sign bit)•(1100 >> 3) = 1111 (-4/8 = -1 ) Floor value of -0.55Examples of Arithmetic Shift 1111 1011 Arithmetic shift right by 1 1111 1101 1111 1011 Arithmetic shift left by 1 1111 0110 1011 1111 (= -65) Arithmetic shift left by 1 (i.e. x2) 0111 1110 (= +126 -130) Underflow ! 0100 0010 (= +66) Arithmetic shift left by 1 (i.e. x2) 1000 0100 (= -124 +132) Overflow !Overflow/Underflow64-bit Logical ShifterS1 S0 D3 D2 D1 D00 X A3 A2 A1 A01 0 0 A3 A2 A11 1 A2 A1 A0 0A3A2 A1 A0D3D2 D1 D0S/NSS0S1L/R101010001201111101301212201313ASSAS DASS ASS AS DASSASSAS DASSASD74-bit Logical Shifter using 4-to-1 Mux4-to-1 Mux0001 10 11s1s0S1 S0 D3 D2 D1 D00 X A3 A2 A1 A01 0 0 A3 A2 A11 1 A2 A1 A0 0D3A2A34-to-1 Mux0001 10 11s1s0D2A14-to-1 Mux0001 10 11s1s0D1A04-to-1 Mux0001 10 11s1s0D0S1S0Right Shift Left Shift84-bit Arithmetic Shifter w/ 4-to-1 Mux4-to-1 Mux0001 10 11s1s0S1 S0 D3 D2 D1 D00 X A3 A2 A1 A01 0A3A3 A3 A2 A11 1 A2 A1 A0 0D3A2A34-to-1 Mux0001 10 11s1s0D2A14-to-1 Mux0001 10 11s1s0D1A04-to-1 Mux0001 10 11s1s0D0S1S0Right Shift Left Shift94-bit Arithmetic Shifter w/ 4-to-1 Mux4-to-1 Mux0001 10 11s1s0S1 S0 D3 D2 D1 D00 X A3 A2 A1 A01 0A3A3 A3 A2 A11 1 A2 A1 A0 0D3A2A34-to-1 Mux0001 10 11s1s0D2A14-to-1 Mux0001 10 11s1s0D1A04-to-1 Mux0001 10 11s1s0D0S1S0Right Shift Left ShiftOverflow/Overflow/UnderflowUnderflow104-bit Arithmetic Shifter w/ 4-to-1 Mux4-to-1 Mux0001 10 11s1s0S1 S0 D3 D2 D1 D00 X A3 A2 A1 A01 0A3A3 A3 A2 A11 1 A2 A1 A0 0D3A2A34-to-1 Mux0001 10 11s1s0D2A14-to-1 Mux0001 10 11s1s0D1A04-to-1 Mux0001 10 11s1s0D0S1S0Right Shift Left ShiftOverflow/Overflow/UnderflowUnderflowOverflowUnderflow Detection11RotatorS1 S0 D3 D2 D1 D00 0 A3 A2 A1 A00 1 A0 A3 A2 A11 0 A1 A0 A3 A21 1 A2 A1 A0 A34-to-1 Mux0001 10 11s1s0D3A2A34-to-1 Mux0001 10 11s1s0D2A14-to-1 Mux0001 10 11s1s0D1A04-to-1 Mux0001 10 11s1s0D0S1S012Barrel Shifter S2 S1 S0 D3 D2 D1 D00 0 0 A3 A2 A1 A00 0 1 A3 A3 A2 A10 1 0 A3 A3 A3 A20 1 1 A3 A3 A3 A31 0 0 A3 A2 A1 A01 0 1 A2 A1 A0 01 1 0 A1 A0 0 01 1 1 A0 0 0 0Shift multiple bitsmultiple bits at a timeLeft ShiftRight Shift13Barrel Shifter Design w/ Mux (D3)S2 S1 S0 D3D2D1D00 0 0 A3 A2 A1 A00 0 1 A3 A3 A2 A10 1 0 A3 A3 A3 A20 1 1 A3 A3 A3 A31 0 0 A3 A2 A1 A01 0 1 A2 A1 A0 01 1 0 A1 A0 0 01 1 1 A0 0 0 04-to-1 Mux0001 10 11s1s00001 10 11s1s04-to-1 Mux2-to-1 Mux2-to-1 Mux10D3A3A3A2 A1 A0S0S1S2Replicate and change wiring of the two 4-to-1 Muxes for D2, D1 and D014Barrel Shifter Design Alternative (16-bit)23 Shifter22 Shifter21 Shifter20 ShifterLeft/RightS3S2S1S016161616(S3 S2 S1 S0) specifies the “shift amount” in binary(S3 S2 S1 S0) specifies the “shift amount” in binary16Output NumberOutput NumberInput NumberInput Number15Barrel Shifter Design w/ nMOSFETD3D2D1D0A3S=0(No Shift)S=1 S=2 S=3A2A1A0S=3S=2S=116A3A3A3Barrel Shifter Design w/ nMOSFETD3D2D1D0A3S=0(No Shift)S=1 S=2S=2 S=3A2A1A0S=3S=2S=2S=1A3A217Barrel Shifter Design w/ nMOSFETD3D2D1D0A3S=0(No Shift)S=1S=1 S=2 S=3A2A1A0S=3S=2S=1S=1= A3= A3= A2= A118Unsigned Binary Multiply 101 (5)X 111 (7)---------- 101 101 101----------100011 (35)19Unsigned Integer Multiplier (2-bit)s00100111101100010101ba baba ba ba baba ba b b xa a 2-bit by 2-bitcarrycarry outp0a0b0H.A.p1csa1b0a0b1H.A.csp2p3a1b120Unsigned Integer Multiplier (3-bit) ba ba ba ba ba ba ba ba ba b b b xa a a 2021221011120001020120123-bit by 3-bitp0a0b0s F.A.p1a1b0a0b10coscic F.A.p2sa2b0a1b1coscic F.A.scoscia0b200c F.A.p3a2b1coscic F.A.coscia1b20ssscp4c F.A.coscia2b2p5214-bit Unsigned Integer Multipliera0 b0P0a1 b0a0 b1++0P1a2 b0a1 b1++a0 b2++0P2a3 b0a2 b1++a1 b2++a0 b3++0P3a3 b1++a2 b2++a1 b3++0P4a3 b2++a2 b3++P5a3 b3++P6P7a0 b0++CinCoutSumA BFull AdderFull Addera0b022Propagation Delaya0 b0P0a1 b0a0 b1++0P1a2 b0a1 b1++a0 b2++0P2a3 b0a2 b1++a1 b2++a0 b3++0P3a3 b1++a2 b2++a1 b3++0P4a3 b2++a2 b3++P5a3 b3++P6P71122333344445555666677884x4Delay = 8 adders8x8Delay = 20 adders23a3 b3++P7 P6Carry-Save Multipliera0 b0P0a1 b0a0 b1++0P1a2 b0a1 b1++a0 b2++0P2a3 b0a2 b1++a1 b2++a0 b3++0P3a3 b2++a2 b3++P5a3 b1++a2 b2a1 b3++++0P424Propagation Delay of Carry-Save Multipliera0 b0P0a3 b1++a2 b2a1 b3++a3 b2++a2 b3++P5a3 b3++P7a1 b0a0 b1++0P11122333355664x4Delay = 6 adders8x8Delay = 14 addersa2 b0a1 b1++a0 b2++0P21122a3 b0a2 b1++a1 b2++a0 b3++0P3112233++440P6 P425Signed Binary MultiplyWhen the Multiplicand is negativeWhen the Multiplicand is negative 11101 (-3) 01001 (+9) -------------------- 11111101 00 11101
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