HW-8 Due March 26, 2004 ECE2030a Name____________________________GT# ____________________________p. 1Bring this homework to class on Friday March 26.HW-7. Finite State Machine - Circuit Design1. Design a synchronous circuit with a two-bit counter (output is C1,C0, negative-edge triggered) that counts the number of 1’s in a row (from input X). When X=0,or a third "1" in a row is detected, resets the counter output, C1, C0, to 0,0.Example Input (X) and output (Ci):X: 0 1 1 1 1 0 0 1 0 1 1 0 1 1 1 0C1,C0 0 01 10 00 01 00 00 01 00 01 10 00 01 10 00 00X ---------->Clock ----->Input C0 COUNTERReset C1Input (X) Q Edge-Triggered LatchEnable Clock Q'1HW-8 Due March 26, 2004 ECE2030a Name____________________________GT# ____________________________p. 22. Complete the table below. A “2M x 16” memory has 2M words of 16 bits.MemoryTotal Bits# of addresses# ofaddresslines# of data lines4M x 832M4M2281M x 3232M1M2032128K x 162M128K17161K x 44K1K104B. 3. Show how to connect these 1M x 16 chips to make a 2M by 16 memory.A0-A19A20R/WR/WCSAddr Data2016R/WCSAddr Data201616The inverter is used as a 1:2 multiplexer (one of2 outputs is "1" based on a one-bit binary
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