R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-1SINGLE CYCLE DPU•CHAPTER XIICHAPTER XIISINGLE CYCLE DATAPATH UNITREAD SINGLE CYCLE DATAPATH FREE-DOC ON COURSE WEBPAGER.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-2SINGLE CYCLE DPUINTRODUCTIONSINGLE CYCLE DPU•SINGLE CYCLE DPU-INTRODUCTION•From the previous chapter, we now have a number of datapath elements such as• Register file (RF)• Adder/subtractor unit (AU)• Logical unit (LU)• Shift unit (SU)•The question now is how to take these datapath elements and form a datapath unit (DPU).•The DPU that we will focus on in this chapter is a basic single cycle DPU using a triple bus internal architecture.R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-3SINGLE CYCLE DPUDATAPATH ELEMENTSSINGLE CYCLE DPU•SINGLE CYCLE DPU-INTRODUCTION•For our examples, we will use the following 32-bit type DPU elements.• These allow us to design a 32-bit word computer with 32 registers.• Of course, other word sizes could be used for other designs.ZdiXdoYdoZwaXraYra32323232x32RF5 5 5rweLUABF323232LFen4SUABF323232STen2AUABF323232ena/sRegister FileAdder/ LogicalUnitShiftUnitSubtractorUnit (AU) (SU)(LU)(RF)ClkR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-4SINGLE CYCLE DPUADD/SUBTRACT MACHINESINGLE CYCLE DPU•SINGLE CYCLE DPU-INTRODUCTION-DATAPATH ELEMENTS•Below is a simple datapath with a register file and adder/subtractor.• This structure is also known as a triple bus internal DPU architecture.ZdiXdoYdo32x32RF5 5 5rweAUABena/s323232X busY busZ busClkImportant:It only takes 1clock cycle toadd/subtract andstore the result.DatapathZwaXraYraR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-5SINGLE CYCLE CPUADD/SUBTRACT MACHINESINGLE CYCLE DPU•SINGLE CYCLE DPU-INTRODUCTION-DATAPATH ELEMENTS-ADD/SUBTRACT MACHINE•This simple add/subtract machine DPU allows us to add or subtract values in our registers and store the result back into another register.• For instance, say that we wanted to add the contents of register R1 with register R2 and store the result back in register R3.• What control signals are required?• = 0 and en = 1 for AU.•Xra = 00001, Yra = 00010, Zwa = 00011, and rwe = 1 for RF.• These control signals are applied at the beginning of a clock cycle. The signals then propagate forming the sum at the output of the AU. At the end of the clock cycle, the sum (on Z bus) is clocked into R3.R3 R1 R2+=as⁄R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-6SINGLE CYCLE CPUADD/SUBTRACT MACHINESINGLE CYCLE DPU•SINGLE CYCLE DPU-INTRODUCTION-DATAPATH ELEMENTS-ADD/SUBTRACT MACHINE•What if instead we wanted to perform the following operation.• The control signals required are• = 0 and en = 1 for AU.•Xra = 00001, Yra = 00010, Zwa = 00010, and rwe = 1 for RF.• What is the result of this if the current value of R1=0x00000001 and R2=0x00000003?• The register R2 would be updated at the end of the clock cycle with the value 0x00000004.• Remember, the current value of R2 is put on the X or Y bus, and it is only at the END of the clock cycle that the contents of R2 get changed.R2 R1 R2+=as⁄R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-7SINGLE CYCLE DPUBASIC SINGLE CYCLE DPUSINGLE CYCLE DPU•SINGLE CYCLE DPU-INTRODUCTION-DATAPATH ELEMENTS-ADD/SUBTRACT MACHINE•A more useful single cycle datapath can be as follows.• This structure is still a triple bus internal DPU architecture.ZdiXdoYdo32x32RF5 5 5rweLUABLFen4SUABSTen2AUABena/s323232X busY busZ busClkZwaXraYraR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-8SINGLE CYCLE CPUCOMPUTATION EXAMPLESSINGLE CYCLE DPU•SINGLE CYCLE DPU-DATAPATH ELEMENTS-ADD/SUBTRACT MACHINE-BASIC SINGLE CYCLE DPU•How does this change the additions we were doign earlier?• Say we want to again perform the following addition.• The control signals we would need are• = 0 and en = 1 for AU.•en = 0 for LU.•en = 0 for SU.•Xra = 00001, Yra = 00010, Zwa = 00011, and rwe = 1 for RF.• Notice that we use the same control signals as before, but now include signals to disable the LU and SU during this addition clock cycle.R3 R1 R2+=as⁄R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-9SINGLE CYCLE DPUCOMPUTATION EXAMPLESSINGLE CYCLE DPU•SINGLE CYCLE DPU-ADD/SUBTRACT MACHINE-BASIC SINGLE CYCLE DPU-COMPUTATION EXAMPLES•Another operation we might want to do with this DPU is perform a logical shift of the contents of R15 by a distance indicated in R6.• The control signals required are•en = 0 for AU.•en = 0 for LU.•en = 1 and ST = 00 for SU.•Xra = 01111, Yra = 00110, Zwa = 01111, and rwe = 1 for RF.• Notice that this set of control signals disables the AU and LU while enabling the SU.• The SU is set to do a logical shift with ST = 00.• The distance of the shift is according to what is in R6.• The result is stored back in R15 with Zwa = 01111 and rwe = 1 for RF.R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-10SINGLE CYCLE DPUARITHMETIC LOGIC UNITSINGLE CYCLE DPU•SINGLE CYCLE DPU-ADD/SUBTRACT MACHINE-BASIC SINGLE CYCLE DPU-COMPUTATION EXAMPLES•Since only one of AU, SU, or LU will be active at a time in this architecture, we will combine to form an arithmetic logic unit (ALU).SUABF323232STen2AUABF323232ena/sALUABF323232ena/sLUABF323232LFen4STLF42asl2asl line00 - AU01 - SU10 - LUR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-11SINGLE CYCLE DPUSINGLE CYCLE DPU W/ALUSINGLE CYCLE DPU•SINGLE CYCLE DPU-BASIC SINGLE CYCLE DPU-COMPUTATION EXAMPLES-ARITHMETIC LOGIC UNIT•Using our ALU, the DPU can be redrawn as follows.• This structure is still a triple bus internal DPU architecture.ZdiXdoYdo32x32RF5 5 5rwe323232X busY busZ busALUABena/sSTLF42asl2ClkZwaXraYraR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-12SINGLE CYCLE DPUIMMEDIATE REGISTERSINGLE CYCLE DPU•SINGLE CYCLE DPU-COMPUTATION EXAMPLES-ARITHMETIC LOGIC UNIT-SINGLE CYCLE DPU W/ALU•Many designs also include some form of immediate register.• Allows for operations such as .ZdiXdoYdo32x32RF5 5 5rwe323232X busY busZ busALUABena/sSTLF42asl2Clkimmediate registerim en im va32ZwaXraYraR28 R5 Immediate+=R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER XII-13SINGLE CYCLE DPUIMMEDIATE REGISTERSINGLE CYCLE DPU•SINGLE CYCLE DPU-ARITHMETIC LOGIC UNIT-SINGLE CYCLE DPU W/ALU-IMMEDIATE REGISTER•The im_en line does two things:• When 0, im_en controls•immediate register outputs to go to high impedence so as NOT to affect Y bus.•register file Y data out
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