Slide 1Sequential Logic CircuitsState machine exampleSlide 4Closed-Loop Logic for Storing InformationSR LatchSlide 7Slide 8SR Latch w/ ControlIssue of an SR Latch or SR LatchD LatchD Latch Keeping Data for ReadD Latch Writing Data D10T D Latch w/ Transmission GatesSlide 15Slide 16D Latch SymbolLatch is TransparentTransparency PropertyProblem of TransparencySlide 21Eliminating TransparencyBehavior of Master-Slave LatchesSlide 24Slide 25Slide 26Flip-Flop (F/F)Negative Edge Triggered Flip-FlopPositive Edge Triggered Flip-FlopSlide 30Flip Flops SymbolsDual-phase Non-overlapped ClocksDual-Phase Non-overlapped ClocksECE2030 Introduction to Computer EngineeringLecture 14: Sequential Logic CircuitsProf. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech2Sequential Logic Circuits•Sequential circuits –Combinational logic circuits–State information (stored in memory)•Output is a function of inputs and present state•Can be synchronous or asynchronousCombinationalcircuitsinputsoutputsStorageElementdelaydelayPresent Present StateStateNext Next StateStateController by a periodic clock or an event trigger3State machine exampleA TV channel controlCH 2CH 2CH 3CH 3CH 1CH 10011104Sequential Logic Circuits•Synchronous Circuits use clock pulse to synchronize•For a typical synchronous design, data are latched into the storage upon clock transition (edge-triggered) CombinationalcircuitsinputsoutputsStorageElementPresent Present StateStateNext Next StateStateclock5Closed-Loop Logic for Storing Information10A bufferTpdTpdXX 6SR LatchSSRRQQQQNN7SR LatchS R Q QN0 0 Q Q0 1 0 11 0 1 01 1 0 0SSQQQQNNRRResetSetUndefinedNo Change8SR LatchS R Q QN0 0 1 10 1 1 01 0 0 11 1 Q QRRQQQQNNSSResetSetUndefinedNo Change9SR Latch w/ Control C S R Q QN0 X X Q Q1 0 0 Q Q1 0 1 0 11 1 0 1 01 1 1 1 1QQQQNNRRCCSSResetSetUndefinedNo ChangeNo Change10Issue of an SR Latch or SR LatchSSQQQQNNRRSSRRS R Q QN0 0 Q Q0 1 0 11 0 1 01 1 0 0QQQQNNRace, and UnstableRace, and Unstable11D LatchQQQQNNCCDDC D Q QN0 X Q Q1 0 0 11 1 1 012D Latch Keeping Data for ReadQQQQ13D Latch Writing Data DDDDQQQQ1410T D Latch w/ Transmission GatesDDEnEnEnEnEnEnQQQQ1510T D Latch w/ Transmission GatesDDEn=1En=1EnEnQQQQDDWriting DataDDDDEnEn1610T D Latch w/ Transmission GatesD_newD_newEn=0En=0EnEnQQQQWriting DataDDDDDDEnEn17D Latch SymbolDDEnEnQQQQEn D Q Q0 X NC NC1 0 0 11 1 1 0NC: No Change18Latch is Transparent•D Latch is called “transparent” or “level sensitive”•Output follows input instantaneouslyEnEnDDQQQQTransparent19Transparency PropertyDDEnEnQQTransparent LatchDDEnEnQQStorageCell00DDEnEnQQStorageCell11Latch acts like a WireLatch acts like a Wire20Problem of Transparency•A momentary input change tunnels through the latch and the entire circuitry•What problem this can cause? DDEnEnQQTransparent Transparent LatchLatch Other Logic Other Logic CircuitsCircuits21Problem of TransparencyEnEnTransparent Transparent LatchLatch11DDQQDDEnEnDDQQOscillating Oscillating Unstable UnstableUnstableUnstable22Eliminating Transparency•Separating the input and output, so they are independently controlled•Only open one gate at a time to avoid tunnelingEnEnTransparent Transparent LatchLatchDDQQEnEnTransparent Transparent LatchLatchDDQQ23Behavior of Master-Slave LatchesEnEnDDQQEnEnDDQQ1100StorageCellStorageCell (00)EnEnDDQQEnEnDDQQ0011StorageCell (11)StorageCell24Behavior of Master-Slave LatchesEnEnD1D1Q1Q1EnEnD2D2Q2Q2EnEnD1D1(initialized to1)(initialized to1)D1D1Q1=D2Q1=D2Q2Q2A Toggle Cell, will discuss more later25Behavior of Master-Slave LatchesEnEnD1D1Q1Q1EnEnD2D2Q2Q2EnEnD1D1(input)(input)Q1=D2Q1=D2Q2Q226Behavior of Master-Slave LatchesEnEnD1D1Q1Q1EnEnD2D2Q2Q2EnEnQ1=D2Q1=D2Q2Q2D1D1(input)(input)27Flip-Flop (F/F)D1D1Q1Q1D2D2Q2Q2Enable (or clock)Enable (or clock)InputInputOutputOutputEnable Enable (or clock)(or clock)InputInputOutputOutput1-bit 1-bit Flip FlopFlip Flop28Negative Edge Triggered Flip-FlopD1D1Q1Q1D2D2Q2Q2clockclockInputInputQ1=D2Q1=D2OutputOutputEnable (or clock)Enable (or clock)InputInputOutputOutput29Positive Edge Triggered Flip-FlopD1D1Q1Q1D2D2Q2Q2clockclockQ1=D2Q1=D2Enable (or clock)Enable (or clock)InputInputOutputOutputInputInputOutputOutput30Positive Edge Triggered Flip-FlopD1D1Q1Q1D2D2Q2Q2clockclockQ1=D2Q1=D2Enable (or clock)Enable (or clock)InputInputOutputOutputInputInputOutputOutput31Flip Flops SymbolsDCQQDCQQPositive Edge TriggeredD Flip FlopNegative Edge TriggeredD Flip Flop32Dual-phase Non-overlapped Clocks •In reality, enable control is not ideal•Use dual phase clocks (1 and 2) to replace Enable and its inversion11Q1=D2Q1=D2InputInputOutputOutput22D2 follows 1 while Output follows 233Dual-Phase Non-overlapped ClocksD1D1Q1Q1D2D2Q2Q2InputInputOutputOutputInputInputOutputOutput1-bit 1-bit Flip FlopFlip
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