R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-1SEQUENTIAL SYSTEMS•CHAPTER VIICHAPTER VIISEQUENTIAL SYSTEMS - LATCHES & REGISTERSR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-2SEQUENTIAL SYST.INTRODUCTIONSEQUENTIAL SYSTEMS•SEQUENTIAL SYSTEMS-INTRODUCTION•So far...• So far we have dealt only with combinational logic where the output is formed from the current input.•Sequential systems• Sequential systems extend the idea of combinational logic by including a system state, or in other words memory, to our system.• This allows our system to perform operations that build on past operations in a sequential manner (i.e. one after another).• Timing diagrams will be needed to analyze the operation of many sequential systems.InputCombinationalLogicOutputR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-3SEQUENTIAL SYST.MEALY & MOORE MACHINESSEQUENTIAL SYSTEMS•SEQUENTIAL SYSTEMS-INTRODUCTION•Mealy machine• Sequential system where output depends on current input and state.•Moore machine• Sequential system where output depends only on current state.InputCombinationalLogicMemory(state)OutputSequential SystemInputCombinationalLogicMemory(state)OutputSequential SystemR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-4STORING BITSSTORING A BITSEQUENTIAL SYSTEMS•SEQUENTIAL SYSTEMS-INTRODUCTION-MEALY & MOORE•Since there are propagation delays in real components, this time delay can be used to store information.• For instance, the following buffer has a propagation delay of .tpdtpdAFAFTiming DiagramtpdR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-5STORING BITSFEEDBACK LOOPSSEQUENTIAL SYSTEMS•SEQUENTIAL SYSTEMS•STORING BITS-STORING A BIT•If we wish to store data for an indefinite period of time, then a feedback loop can be used to maintain the bit.• How do we get the bit in there?tpd00tpd11tpd12tpd12Can also use two inverters!R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-6STORING BITSLOADING A BITSEQUENTIAL SYSTEMS•SEQUENTIAL SYSTEMS•STORING BITS-STORING A BIT-FEEDBACK LOOPS•To store a bit, we need a way of loading an input bit into the structure and making/breaking the connection in the feedback look.• One way of breaking connections is to use transmission gates.• gets temporarily stored in the inverters when and . Then setting and , gets held in the feedback loop.QQATGTGS1S2Note: The latch is level-sensitive.If A changes while S1 = 1,then Q will change as well.AS11=S20=S10=S21=AR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-7LATCHESD LATCH (WITH TG)SEQUENTIAL SYSTEMS•STORING BITS-STORING A BIT-FEEDBACK LOOPS-LOADING A BIT•The previous example is a data latch (D latch) if both and are controlled by a single line C as follows.• The control line might be derived from the clock signal, or a signal from the controller/sequencer in the microprocessor.S1S2QQDTGTGCNote: The latch is level-sensitive.If D changes while C = 1,then Q will change as well.(Enable)CR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-8LATCHES LATCH (NAND GATES)SRSEQUENTIAL SYSTEMS•LATCHES-D LATCH (WITH TG)-NAND PRIMITIVES-CONSTRUCTING A LATCH•NAND gates can also be used to create a latch, this time an latch.•Notice that this latch is level-sensitive.SR(set)(reset)QQSRQQ11011100100011111001(after S = 1, R = 0)(after S = 0, R = 1)SRAB00010111NAND1110Recall:R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-9LATCHESSR LATCH (NOR GATES)SEQUENTIAL SYSTEMS•LATCHES-CONSTRUCTING A LATCH-S’R’ LATCH -NAND GATES-MIXED LOGIC EQUIV.•The SR latch also uses feedback to “store” a bit.•Notice that this latch is level-sensitive.SRQQ10R (reset)S (set)QQ00101001AB00010111NOR1000Recall:1100000110(after S = 1, R = 0)(after S = 0, R = 1)R.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-10LATCHESSR LATCH WITH CONTROLSEQUENTIAL SYSTEMS•LATCHES-S’R’ LATCH -NAND GATES-MIXED LOGIC EQUIV.-SR LATCH -NOR GATES•A control line can be added to the latch as follows forming an SR latch• This control line makes it possible to decide when the inputs and are allowed to change the state of the latch.SRQQSRSREnableSRR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-11LATCHESD LATCH (WITH LATCH)SRSEQUENTIAL SYSTEMS•LATCHES-MIXED LOGIC EQUIV.-SR LATCH -NOR GATES-SR LATCH W/ CONTROL•A D latch can be implemented using what is effectively the SR latch with a control line as follows.• Note that as long as , that the latch will change according to the value of .QQSRDEnableC1=DR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-12LATCHESTIMING DIAGRAMSSEQUENTIAL SYSTEMS•LATCHES-SR LATCH -NOR GATES-SR LATCH W/ CONTROL-D LATCH•Timing diagrams allow you to see how a sequential system changes with time using different inputs.• For instance, a timing diagram for a D latch might look like the following.DEnableQQTimeR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-13LATCHESTRANSPARENCY (1)SEQUENTIAL SYSTEMS•LATCHES-SR LATCH W/ CONTROL-D LATCH-TIMING DIAGRAMS•Latches like the D latch are termed “transparent” or level-sensitive.• This is because, when enabled, the output follows the input.DEnableQQNote:TransparentTransparentLatchIN OUTEnableR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-14LATCHESTRANSPARENCY (2)SEQUENTIAL SYSTEMS•LATCHES-D LATCH-TIMING DIAGRAMS-TRANSPARENCY•The following behaviour is observed for Enable = 0 and Enable = 1.IN OUT1IN OUT0StoredTransparentLatchIN OUTEnableWhen Enable = 1,latch acts like wire.When Enable = 0,input disconnected andstored bit outputed.bitR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-15LATCH EXAMPLEPROBLEMS W/ TRANSPARENCYSEQUENTIAL SYSTEMS•LATCHES-D LATCH-TIMING DIAGRAMS-TRANSPARENCY•A problem with latches is that they are level-sensitive.• A momentary change of input changes the value passed out of the latch.•This is a problem if the input of a latch depends on the output of the same latch.• Example: Design a system that flips a stored bit whenever Enable goes high. An inexperienced engineer might design the following.TransparentLatchHow will this design behave?Will the bit flip once when theEnable signal goes high?Answer: The output willfollow the input, whichhappens to keep changing.EnableR.M. Dansereau; v.1.0INTRO. TO COMP. ENG.CHAPTER VII-16LATCH EXAMPLEPROBLEMS W/ TRANSPARENCYSEQUENTIAL SYSTEMS•LATCHES•LATCH EXAMPLE-PROB W/TRANSPARENCY•Let’s analyze the timing behaviour of this “poor” design.ABBA• Notice
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