Slide 11-to-2-Line DecoderN-to-M-Line Decoder (2N M)2-to-4-Line Decoder2-to-4-Line Decoder w/ EnableSlide 63-to-8-Line DecoderSlide 8Slide 9Implementing Logic w/ DecoderBCD-to-7-Segment DecoderSlide 12Slide 13Slide 14BCD-to-7-Seg. Decoder Truth TableDesign Each Output Individually “a”Design Each Output Individually “b”M-to-N-Line Encoder (M2N)4-to-2 Encoder8-to-3 EncoderExample 1 of an EncoderExample 2 of an Encoder8-to-3 Priority Encoder4-to-2 Priority EncoderSlide 25Slide 264-to-2 Priority Encoder Schematic8-to-3 Priority Encoder (A2)8-to-3 Priority Encoder (A1)8-to-3 Priority Encoder (A0)8-to-3 Priority Encoder (All)1-bit Magnitude Comparator2-bit Magnitude Comparator (unsigned)Slide 343-bit Magnitude Comparator (unsigned)4-bit Magnitude Comparator (unsigned)4-bit Magnitude ComparatorCascading Comparator16-bit Cascading ComparatorECE2030 Introduction to Computer EngineeringLecture 11: Building Blocks for Combinational Logic (2) Decoders/Encoders, ComparatorsProf. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech21-to-2-Line DecoderADAD10AAD1D1D0D00 0 11 1 0D0D1A3N-to-M-Line Decoder (2N M)A1 A0 D3 D2 D1 D00 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0D0D1D2D32-to-42-to-4-line-linedecoderdecoderA0A142-to-4-Line DecoderA1 A0 D3 D2 D1 D00 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0013012011010AADAADAADAADHow about if no one should be enabled ?A1A0D0D1D2D352-to-4-Line Decoder w/ EnableEnA1A0D3D2D1D00 X X 0 0 0 01 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 0013012011010AEnADAEnADAAEnDAAEnDD0D1D2D32-to-42-to-4-line-linedecoderdecoderA0A1En62-to-4-Line Decoder w/ EnableEnA1A0D3D2D1D00 X X 0 0 0 01 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 0013012011010AEnADAEnADAAEnDAAEnDA1A0D0D1D2D3En73-to-8-Line DecoderA2A1A0D7D6D5D4D3D2D1D00 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0Truth Table83-to-8-Line DecoderA2A1A0D7D6D5D4D3D2D1D00 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0Truth Table93-to-8-Line DecoderA2 A1 A0 D7 D6 D5D4 D3 D2 D1D00 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0D0D1D2D32-to-42-to-4-line-linedecoderdecoderA0A1EnD0D1D2D3D0D1D2D32-to-42-to-4-line-linedecoderdecoderA0A1EnD4D5D6D7A0A1A210Implementing Logic w/ DecoderD0D1D2D33-to-83-to-8-line-linedecoderdecoderA0A1A2D4D5D6D75,7)M(0,1,2,3,Z)Y,F2(X,m(1,2,6,7)Z)Y,F1(X,XXYYZZF1F1F2F211BCD-to-7-SegmentDecoderBCD-to-7-Segment Decoder•Another kind of decoder a b c d e f g aa bb cc dd ee ff ggAABBCCDD12BCD-to-7-SegmentDecoderBCD-to-7-Segment Decoder•Another kind of decoder a b c d e f g aa bb cc dd ee ff ggAABBCCDDabcdegf13BCD-to-7-SegmentDecoderBCD-to-7-Segment Decoder•Decode “2” and show a b c d e f g aa bb cc dd ee ff ggAABBCCDDabcdegf0010110111014BCD-to-7-SegmentDecoderBCD-to-7-Segment Decoder•Decode “4” and show a b c d e f g aa bb cc dd ee ff ggAABBCCDDabcdegf0100011001115BCD-to-7-Seg. Decoder Truth TableA B C D a b c d e f g0 0 0 0 0 1 1 1 1 1 1 01 0 0 0 1 0 1 1 0 0 0 02 0 0 1 0 1 1 0 1 1 0 13 0 0 1 1 1 1 1 1 0 0 14 0 1 0 0 0 1 1 0 0 1 15 0 1 0 1 1 0 1 1 0 1 16 0 1 1 0 0 0 1 1 1 1 17 0 1 1 1 1 1 1 0 0 0 08 1 0 0 0 1 1 1 1 1 1 19 1 0 0 1 1 1 1 0 0 1 1>10All other inputs 0 0 0 0 0 0 016Design Each Output Individually “a”A B C D a0 0 0 0 0 11 0 0 0 1 02 0 0 1 0 13 0 0 1 1 14 0 1 0 0 05 0 1 0 1 16 0 1 1 0 07 0 1 1 1 18 1 0 0 0 19 1 0 0 1 1>10All other inputs 000 01 11 10001 0 1 1010 1 1 0110 0 0 0101 1 0 0ABCDCBABDACDADBAa 17Design Each Output Individually “b”A B C D b0 0 0 0 0 11 0 0 0 1 12 0 0 1 0 13 0 0 1 1 14 0 1 0 0 15 0 1 0 1 06 0 1 1 0 07 0 1 1 1 18 1 0 0 0 19 1 0 0 1 1>10All other inputs 000 01 11 10001 1 1 1011 0 1 0110 0 0 0101 1 0 0ABCDCDADCABACBb 18M-to-N-Line Encoder (M2N)D0D1D2D32-to-42-to-4-line-lineDecoderDecoderA0A1EnD0D1D2D34-to-24-to-2-line-lineEncoderEncoderA0A1Ac194-to-2 EncoderD3 D2 D1 D0 A1 A00 0 0 1 0 00 0 1 0 0 10 1 0 0 1 01 0 0 0 1 1Since Dx=1 only in one column at a time A0 = D1 + D3A1 = D2 + D300 01 11 1000X 0 X 1010 X X X11X X X X101 X X XD3 D2D1 D0D0D2or D3D1A0 For A000 01 11 1000X 0 X 0011 X X X11X X X X101 X X XD3 D2D1 D0D0D1or D3D2A1 For A1208-to-3 EncoderD7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A00 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 10 0 0 0 0 1 0 0 0 1 00 0 0 0 1 0 0 0 0 1 10 0 0 1 0 0 0 0 1 0 00 0 1 0 0 0 0 0 1 0 10 1 0 0 0 0 0 0 1 1 01 0 0 0 0 0 0 0 1 1 1Since Dx=1 only in one column at a time A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D721Example 1 of an EncoderOnly point to one single reading at a time.22Example 2 of an EncoderD0D1D2D38-to-38-to-3-line-lineEncoderEncoderA0A1A2D4D5D6D7AmyBrianCathyDaveEllenFrankGinaHughAc0000Activeor not1101???1238-to-3 Priority EncoderD7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Active0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 10 0 0 0 0 0 1XX 0 0 1 10 0 0 0 0 1XXXX 0 1 0 10 0 0 0 1XXXXXX 0 1 1 10 0 0 1XXXXXXXX 1 0 0 10 0 1XXXXXXXXXX 1 0 1 10 1XXXXXXXXXXXX 1 1 0 11XXXXXXXXXXXXXX 1 1 1 1244-to-2 Priority EncoderD3 D2 D1 D0 A1 A0 Active0 0 0 0 0 0 00 0 0 1 0 0 10 0 1XX 0 1 10 1XXXX 1 0 11XXXXXX 1 …
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