ECE2030b - HW-5 v.2 Due Monday 10/21 during class. - ANSWERSProblem 1. Using Finite State Machine techniques, design a circuit to: Detect when sequential input X delivers 3 logic 1's in a row. Do not detect overlapping sequences.Example: Input: 01101111011111001111110 Output: 00000010000100000010010A. Draw a State Diagram showing all possible states and transitions.B. Draw a logic table for the Next State bits (Ni) and the Output bit (Q), as afunction of Present State bits (Pi) and Input bit (X).C. Draw Karnaugh maps for the separate outputs, Ni and Q.D. Draw a logic diagram showing the necessary registers and combinatorial logicblocks.A. State Diagram (Meely)State Diagram (Moore)No new 1’sseen.State 00Output 0One new 1seen.State 01Output 0Two new1’s seen.State 10Output 00Three new1’s seen.State 11Output 10011110No new 1’sseen.State 00One new 1seen.State 01Two new1’s seen.State 101 / 01 / 00 / 0 , 1 / 1UnusedState 11X / 00 / 00 / 0Check List: Does every state have exits defined for all inputs(0,1)?B. Logic or Truth Tables:MeelyPresentStateInputNextStateOutput*P1P0XN1N0Q000000001010010000011100100000101001110000111000• For Meely Machine, output occurs while machine is in state 10and X=1.Moore Machine:MoorePresentStateInputNextStateOutput*P1P0XN1N0Q000000001010010000011100100000101110110001111011For Moore Machine, output occurs while machine is in state 11. Logicfor Q can be designed as a function of N1,N0B. Karnaugh Maps for Moore Machine:N1: X \ P1,P0000111100000010101N1 = X ( P1’ P0 + P1 P0’) = X ( P1 XOR P0 )N0: X \ P1,P0000111100000011011N0 = X ( P0’ + P1)Q: P1 \ P001000101Q = P0 P1 (note: for Moore Machine, Q is function of presentstate (P1,P0).D. Logic Diagram (Moore)Solution as a Meely Machine is also acceptable.N1 P1P1’ClockN0
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