ECE 2030 Introduction to Computer Engineering March 28 2001 EXAM 2 Page 1 of 5 Name Student Number 1 Check that your exam includes all 5 pages 2 PRINT your name and student number in the spaces above 3 Read all instructions and problems carefully Points will be deducted for failure to follow instructions 4 Show ALL of your work on these pages If you need extra space for a particular problem write on the back of the previous page 5 You are NOT permitted to use notes books calculators or other resources during this exam 6 This exam lasts for 75 minutes Point values are listed for each problem to assist you in best using your time Problem 1 20 points possible Problem 2 9 points possible Problem 3 11 points possible Problem 4 10 points possible TOTAL 50 points possible ECE 2030 Introduction to Computer Engineering February 7 2001 EXAM 1 Page 2 of 5 Problem 1 20 points A 10 points Each row in the table below lists a decimal value and its binary representation in both 6 bit sign magnitude and 6 bit 2 s complement formats Complete the table filling in the missing entries in each row Value decimal 6 bit sign magnitude binary representation 6 bit 2 s complement binary representation 23 101010 5 011010 110110 B 6 points Perform each of the following additions using 6 bit 2 s complement integer arithmetic Write your answers in the boxes provided for each problem and circle the answers indicating the value of the carry out bit and whether or not overflow occurred 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 carry out 0 1 carry out 0 1 carry out 0 1 overflow yes no overflow yes no overflow yes no C 4 points Perform the following subtraction using 6 bit 2 s complement integer arithmetic Write your answer in the box provided and circle the answer indicating whether or not overflow occurred 1 0 1 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 overflow yes no overflow yes no ECE 2030 Introduction to Computer Engineering February 7 2001 EXAM 1 Page 3 of 5 Problem 2 9 points A 3 points A function is defined by the truth table at the right On the line below write an expression for a minimal sum ofproducts implementation of this function In the Karnaugh map circle the product terms used in your implementation CD 00 01 11 10 00 1 1 1 0 01 1 0 1 1 11 1 0 0 1 10 0 1 0 0 00 01 11 10 00 1 1 0 1 01 0 0 0 1 11 1 0 1 0 10 1 1 0 1 00 01 11 10 00 1 1 0 1 01 1 0 0 1 11 1 0 0 0 10 0 1 0 1 AB F A B C D B 3 points A function is defined by the truth table at the right On the line below write an expression for a minimal sum ofproducts implementation of this function In the Karnaugh map circle the product terms used in your implementation CD AB G A B C D C 3 points A function is defined by the truth table at the right On the line below write an expression for a minimal productof sums implementation of this function In the Karnaugh map circle the sum terms used in your implementation H A B C D CD AB ECE 2030 Introduction to Computer Engineering February 7 2001 EXAM 1 Page 4 of 5 Problem 3 11 points A 5 points A circuit is to be designed that generates a single 1 each time it detects the sequence 110 This sequential circuit has one input X and one output Z Complete the state diagram below labeling the outputs for the transition arcs already shown and adding and labeling any additional states and or transitions arcs needed You should attempt to minimize the number of states used Assume that state A is the initial state key X Z 0 1 A S 1 B C B 6 points A two phase clocked register flip flop is to be designed This register has two clock inputs phi1 phi2 two control inputs LOAD INV one data input D and one output Q The logical behavior of this register is described by the truth table at the right Q is the next state of the register LOAD INV Q 0 0 Q 0 1 Q 1 0 D 1 1 D The register is to be designed using two clocked latches already drawn below and some combination of INVERTERs 2 input NANDs and 2 input XORs You are not required to use all of these gate types and you may use as many of each type as you choose Complete the schematic below for this circuit clearly labeling all of the inputs and the output You should make a reasonable effort to minimize circuit complexity IN OUT IN OUT CLK CLK phi1 phi2 ECE 2030 Introduction to Computer Engineering February 7 2001 EXAM 1 Page 5 of 5 Problem 4 10 points A A 3 bit counter whose outputs are labeled Q3 Q2 and Q1 is to be designed to count in a Gray Code sequence as follows Q3Q2Q1 000 001 101 100 110 111 011 010 000 The two inputs to this circuit aside from the clocks are Count Enable CE and Clear CLR You may implement this circuit using either D register cells or toggle register cells 1 bit counters as the basic building block Check the appropriate line below to indicate your choice Draw the schematic for your circuit It is not necessary to show the internal circuitry of your registers just draw their symbols or the clock lines You may use any of the basic logic gates to implement the remaining circuitry You MUST provide sufficient work to clearly show how you derived your circuit D register D Clear Q toggle register 1 bit counter CE Clear Out
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