ECE 2030 Introduction to Computer Engineering April 20 2011 EXAM 2 Page 1 of 6 Name Student Number 1 Check that your exam includes all 6 pages 2 PRINT your name and student number in the spaces above 3 Read all instructions and problems carefully Points may be deducted for failure to follow instructions 4 Show ALL of your work on these pages If you need extra space for a particular problem write on the back of the previous page 5 You are NOT permitted to use notes books calculators or other resources during this exam 6 This exam lasts for 75 minutes Point values are listed for each problem to assist you in best using your time Problem 1 18 points possible Problem 2 14 points possible Problem 3 18 points possible Problem 4 13 points possible Problem 5 12 points possible TOTAL 75 points possible ECE 2030 Introduction to Computer Engineering April 20 2011 EXAM 2 Page 2 of 6 Problem 1 18 points A 4 points Each row in the table below lists a decimal value and its binary representation in both 6 bit sign magnitude and 6 bit 2 s complement representations Complete the table filling in the missing entries in each row Value decimal 6 bit sign magnitude binary representation 6 bit 2 s complement binary representation 19 011011 101011 101011 B 9 points Perform each of the following additions using 6 bit 2 s complement integer arithmetic Write your answers in the boxes provided for each problem and circle the answers indicating the value of the carry out bit and whether or not overflow occurred 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 0 1 0 1 carry out carry out carry out 0 1 overflow yes no 0 1 overflow yes no 0 1 overflow yes no C 5 points Perform the following subtraction using 6 bit 2 s complement integer arithmetic Write your answer in the box provided and circle the answer indicating whether or not overflow occurred 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 overflow yes no overflow yes no ECE 2030 Introduction to Computer Engineering April 20 2011 EXAM 2 Page 3 of 6 Problem 2 14 points A 2 points A clearable D register that uses two phase non overlapping clocking has the logic symbol shown at the right and the schematic shown below Complete the state table below right for this register IN OUT CLR 1 2 IN D Q D Q OUT CLR CLR 1 IN OUT 2 B 6 points Complete the following timing diagram for this register calculating the value of the register output OUT and the value of the line between the two latches MID Assume that the initial value of the output is zero 1 2 CLR IN MID OUT C 6 points Complete the timing characteristic diagram for this register 1 2 CLR IN OUT ECE 2030 Introduction to Computer Engineering April 20 2011 EXAM 2 Page 4 of 6 Problem 3 18 points A finite state machine with a single input X and a single output Z is defined by this state table A A 4 points In the space below draw the state diagram for this FSM B C D B 1 point What type of FSM is this circle one S1 S0 S1 S0 X 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 1 1 1 Mealy Z Moore C 9 points This FSM will be implemented using D flip flops Complete the Karnaugh maps and derive minimal SOP or POS equations for the flip flop inputs and the output X S1S0 0 1 S1S0 X 0 1 S1S0 X 00 00 00 01 01 01 11 11 11 10 10 10 D1 D0 0 1 Z D1 D0 Z D 4 points Complete the table below showing the sequence of states and the output values that will be generated by this FSM given the input sequence shown and starting in state A Input X 0 Current State A Output Z 1 0 1 1 0 0 1 ECE 2030 Introduction to Computer Engineering April 20 2011 EXAM 2 Page 5 of 6 Problem 4 13 points A 6 points A 4 to 1 multiplexer shown to the right can be used to implement any arbitrary combinational logic function of input bits X and Y For each row in the table below specify the values 0 or 1 that should be assigned to inputs LF0 LF1 LF2 and LF3 to implement the logic function listed in the first column FUNCTION LF0 LF1 LF2 LF0 I0 LF1 I1 LF2 I2 LF3 I3 LF3 X OUT S1 S0 X Y X Y X Y exclusive OR B 4 points A function is defined by the truth table given below Draw the schematic for a circuit implementing this function using either a 4 to 1 multiplexer or a 3 to 8 decoder as the key component along with additional logic gates as needed A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 1 0 1 1 0 0 C 3 points An 8 to 3 priority encoder shown at right is designed such that I0 has the highest priority and priorities decrease sequentially to I7 as the lowest priority For each row in the table below list the encoder inputs I0 I7 that will produce the indicated output values D2D1D0 Use don t care inputs to show multiple possible values I0 I1 I2 I3 I4 I5 I6 I7 D2D1D0 101 010 I0 I1 I2 I3 I4 I5 I6 I7 D2 D1 D0 ECE 2030 Introduction to Computer Engineering April 20 2011 EXAM 2 Page 6 of 6 Problem 5 12 points A 6 points Each row in the following table describes a different memory system configuration Fill in all of the missing entries NOTE K 210 M 220 G 230 Memory Configuration Total bits in memory of memory address lines 235 x 32 24 of memory data lines Size of individual memory ICs 8 1G x 1 Number of memory ICs needed 2M x 8 B 6 points Complete the schematic below for the implementation of a 512M x 8 memory system using four 256M x 4 memory chips Clearly label the address bus data bus and control signals Fill in the blanks below with the size of the address and data buses Number of bits in system address bus Number of bits in system data bus Number of address bits for each chip Number of data bits for each chip A A D A D R W CE D A R W …
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