Department of Electrical Engineering and Computer ScienceArea CalculationGradingUNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R. W. Brodersen Design Problem 1 EECS 140 Mike Chen (Due 2/12/04) Spring 2004 1. Design Specification You are asked to design a CMOS amplifier with a gain of at least 500, while driving a resistive load, shown in Figure 1. The available circuit components are NMOS transistors, PMOS transistors or resistors. Ideal sources can only be used to generate the supply voltages, not to generate bias currents or voltages. The design specifications are as following, - Lmin = 0.13µm, Wmin,nmos = 0.15µm, Wmin,pmos = 0.15µm; - Vdd = 1.2 V, Vss = 0 V; - RL = 50Ω; - Vout biasing point 0.5~0.7 V; - Vin biasing point (Vic) 0.35~0.85 V; - Total gain Vout/Vid >= 500. The design goal is to minimize the following figure of merit (Watts*µm2), AreaPowerFOM⋅= VoutVidVicVddVssRL Figure 12. Area Calculation Calculate the area by adding up the gate area (W*L) of all the transistors and the area of the resistors. For the transistors, the minimum L is 0.13 µm and the minimum W is 0.15 µm. For the resistors, the minimum W and L are 0.5 µm; the sheet resistance is 250Ω/square. You are allowed to tie the bulk of any transistor to the source instead of to the positive or negative supply, but at the cost of an area penalty. If you choose to tie the bulk to the source, the area of the transistor should be doubled. 3. Device Models http://bwrc.eecs.berkeley.edu/classes/ee140/dp/model_ee140.sp The device models are encapsulated in a sub-circuit; use: x1 d g s b nmos w=10u l=0.13u x2 d g s b pmos w=10u l=0.13u to instantiate an NMOS and a PMOS transistor respectively (you have to use the prefix ‘x’ instead of ‘m’). The reason for using a subcircuit is to allow λ to decrease with increasing transistor length. The output resistance parameter λ will stay the same as before for minimum length transistors (Lmin=0.13µm), but will decrease with increasing L (drawn L, not effective L). Since the output resistance is proportional to 1/ λ, the output resistance increases with increasing L. Since we are using level-2 device model, it is worthwhile to calculate level-1 parameters of the device model for your hand calculations. (Ref: problem 1 of HW1, extracting K’, λ, γ, etc.) 4. Run testbench Perform dc operation point and small-signal transfer function analysis. Usage: put testbench_dp1.sp, model_ee140.sp, circuit.sp in the same directory and run ‘hspice testbench_dp1.sp –o testbench_dp1’. 5. What to include in your report http://bwrc.eecs.berkeley.edu/classes/ee140/dp/guidelines_dp1.pdf 6. Grading 100 points total: 45 points for conciseness and clearness of the report 45 points for meeting the specifications 10 points for how well FOM is
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