EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2011 C Nguyen PROBLEM SET 3 Issued Tuesday Feb 8 2011 Due Tuesday Feb 15 2011 5 00 p m in the EE 140 homework box in 240 Cory 1 Multi stage analysis Fig PS3 1 shows a three stage amplifier in which the stages are directly coupled The amplifier however utilizes bypass capacitors and as such its frequency response falls off at low frequencies For our purpose here we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest a Find the dc bias current in each of the three transistors Also find the dc voltage at the output Assume VBE 0 7V 100 and neglect the Early effect b Find he input and output resistance c Use the current gain method to evaluate the voltage gain vo vi d Find the high frequency pole formed at the interface between the first and the second stages Assume that C 2 2pF and C 2 10pF Fig PS3 1 EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2011 C Nguyen 2 Cascode stage analysis The ac schematics of a common source stage and a cascode stage are shown in Fig PS3 2 with RS 10 k and RL 20 k Using the transistor and operating point data below a Calculate the low frequency small signal voltage gain vo vi for each circuit b Calculate the 3 dB frequencies of the two circuits Data ID 0 5 mA W 100 m Ldrwn 2 m Ld 0 2 m Xd 0 0 k n 60 A V2 0 Csb Cdb 0 Cox 0 7 fF m2 and Cgd 14 fF M2 RS RL RS M1 vi RL M1 vi Fig PS3 2 3 Single stage design Use the following parameters nCox 100 A V2 pCox 50 A V2 VT 0 5 V VDD 3 V L 1 m Wp 2 Wn VGS VT min 100 mV for strong inversion CL 4 pF Cgs 1 pF Cgd 0 pF Cdb 1 pF a What is the maximum midband voltage gain of a resistively loaded common source amplifier operating in strong inversion Use n p 0 b How about with an active PMOS load n p 0 1 V 1 c If ID 1 mA how would you size each of the devices d With ID 1 mA what is the dominant pole frequency of each of these amplifiers EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2011 C Nguyen 4 PNP input active load stage analysis An amplifier is shown in Fig PS3 4 IB is adjusted such that VO 0 V dc VSUPPLY 10 V Calculate the low frequency small signal transresistance vo vi and estimate the 3 dB frequency npn 100 fT 500 MHz at IC 1 mA C 0 0 7 pF Cje 3 pF at the bias point Ccs0 2 pF rb 0 and VA 120 V Assume n 0 5 and 0 0 55 V for all junctions pnp 50 fT 4 MHz at IC 0 5 mA C 0 1 0 pF Cje 3 pF at the bias point Cbs0 2 pF rb 0 and VA 50 V Assume n 0 5 and 0 0 55 V for all junctions VSUPPLY Q1 IB ii Q2 Q3 30 k VSUPPLY Fig PS3 4
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