EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O 1 Output Stages University of California Berkeley Large Signal Swing Distortion Power Efficiency College of Engineering Department of Electrical Engineering and Computer Science Robert W Brodersen Typical OP Amp EECS140 VOLTS Analog Circuit Design Lectures on OUTPUT STAGES EECS140 ANALOG CIRCUIT DESIGN V OLTS x 100 1000 X50 RL DIFF PAIR LECTURES ON OUTPUT STAGES O 2 Power LECTURES ON OUTPUT STAGES Typically output load is low impedance but not always If it is a source follower is a possible output stage out out desired plus swing out desired neg swing RREF VIN VDD M1 M1 VOUT m3 M3 M2 M2 IQ VDD O 3 1 A max 1 VDD IQ MAX P P GAIN STAGES OUTPUT STAGE EECS140 ANALOG CIRCUIT DESIGN Total power from supplies P SUPPLY Power into Load P LOAD P LOAD Efficiency P SUPPLIES out 1 1 1 RL VIN VOUT IQ VDD RL EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES LECTURES ON OUTPUT STAGES O 4 V DD V DD V To V DSAT V DD IQ RL V DD V DSAT EECS140 ANALOG CIRCUIT DESIGN O 5 1 V out I Q RL 2 V DD V T V DSAT V DD V T R REF IQ IQ V IN W To set use Vout L 2 V DSAT V GS V T V DSAT V DD V OUT V OUT MAX V DD V T V DSAT V OUT MIN V DSAT V DD 3 are the absolute maximum swings in the positive and negative directions Find the W L of M1 V OUT 1 I DS1 I Q I L I Q RL Vout Vout are the desired positive and negative swings They typically should be equal for symmetric outputs EECS140 ANALOG CIRCUIT DESIGN 2 I 1 W Q 2 L 2 k V DD V OUT LECTURES ON OUTPUT STAGES EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O 6 k W V OUT 1 V DD V OUT 1 V T 2 I Q RL 2 L 1 4 e g V OUT 1 2 I Q RL W L 1 k V DD V OUT 1 V T 2 R L 300 V DD 5V V OUT 1 V OUT I Q 10ma O 7 g m R L r o gm RL GAIN 1 g m R L r o 1 g m R L 1 R OUT R L gm 1 3V 3 0 7 R REF 230 10ma 1 2 10 2 W 6 2 56 L 2 90 10 5 3 2 2 10 2 W 263 L 1 90 10 6 5 3 0 7 2 1 2 W g m 2 k I DS 2 90 10 6 263 10 2 2 22 10 3 L 1 45 gm 300 RL 0 87 GAIN 45 300 1 R L gm 1 R OUT R L 45 300 40 gm EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O 8 Power V SUPPLY CurrentOut Power Vout 0V EECS140 ANALOG CIRCUIT DESIGN V OFFSET V IN LECTURES ON OUTPUT STAGES O 9 V OUT 0V IQ 22 I DS W k L 1 DC Power without any Signal V IN V GS1 V TO 3 Power I M3 V DD I M2 V DD I M1 V DD 2 10 10 0 7 1 6V 90 10 6 263 V 3 I Q V DD 3 10 10 3 5 150mW Efficiency Sine Wave 4 IQ V O V O PeakVoltage Average 3 I Q V OUT Power to Load Efficiency 3 I Q V DD 2 IQ VO EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O 10 I M1 2I Q 1 1 1 P L V O I O I Q R L I Q I 2Q R L 2 2 2 1 4 10 300 15mW 2 EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES OUTPUT STAGE SOURCE FOLLOWER 96 02 18 12 03 26 2 9935 O 11 SF SW0 VOUT 2 50 V OUT 1 V OUT I M1 I Q I RL I Q RL IQ IQ RL V OUT 1 V OUT 2 0 VOUT 1 50 1 0 0 500 0M TC 2 I Q V DD P SUPPLY 1 I DS m1 V DD dt TC 0 I Q V DD 3 I Q V DD 150mW P LOAD 15mW Efficiency 10 TotalPower 150mW 1 I 2Q R L 1 I Q R L 2 16 MAX 3 I Q V DD 6 V DD V O L T 0 500 0M L I N 1 0 1 50 2 0 2 50 3 0 5 0 4 0 2 0 VOLTS LIN 0 2 0 VIN 4 0 5 0 output stage source follower Bipolar V BE V CC options nomod name drain gate source bulk model m1 vdd vin vout vout nch l 1u w 263u m2 vout d3 vdd vdd nch l 1u w 56u m3 d3 d3 vdd vdd nch l 1u w 56u rref 0 d3 230 iload vout vdd 1ma rload 0 vout 300 vin vin 0 1 6 vdd vdd 0 5 0 vdd vdd 0 5 0 initial operating point makes it do the power calculation Small signal transfer characterisitcs dc vin 5 5 1 print dc i m1 i m2 i m3 v vout op tf v vout 0 vin measure tot power avg power sweep the input voltage option nopage post 2 absi 1e 10 reli 1e 4 absmos 1e 8 relmos 1e 4 absv 1e 6 relv 1e 4 model pch pmos level 1 tox 170 vto 0 7 kp 30 0e 6 lambda 0 01 gamma 0 5 phi 0 6 capop 0 cgso 3 e 11 cgdo 3 e 11 cgbo 4 e 10 cj 6e 4 reading file bobtools commercial hspice hspice ini model nch nmos level 1 tox 170 vto 0 7 kp 90 0e 6 lambda 0 01 gamma 0 5 phi 0 6 capop 0 cgso 5 e 10 cgdo 5 e 10 cgbo 4 e 10 cj 1e 4 V CESAT V CC I Q R L 865 0433m 1 000e 20 38 2335 R L 300 M1 V IN V DD I I V BE V Th ln C 0 06 log C IS IS M1 Linear 1 5 0 6 15 6 5 R V BE VT IC IS e V DD V DSAT1 V DD V OUT IQ V DD V DD V T V DD 1 P L V CC V BE I Q R L 2 0V V DD M2 M3 1 V CC V BE I Q R L 2 1 V CC V BE Efficiency 3 I Q V CC V CC 6 V CC v vout vin input resistance at vin output resistance at v vout Inverter Output Stage V CC V BE V DD IQ RL V DSAT2 for symmetry V MAX V CC V BE V MAX 1 O 15 More voltage range O 14 Bipolar Cont V CC …
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