EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGESUniversity of CaliforniaBerkeleyCollege of EngineeringDepartment of Electrical Engineeringand Computer ScienceRobert W. BrodersenEECS140Analog Circuit Design LecturesonOUTPUT STAGESEECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGESOutput Stages O-1Large Signal SwingDistortionPowerEfficiencyTypical OP Amp :11×µVOLTSVOLTSx 100- 1000RLDIFF PAIR GAIN STAGESOUTPUT STAGE+-X50EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-2νout1+MAXPP–Total power from supplies = PSUPPLYPower :Power into Load = PLOADEfficiencyPLOADPSUPPLIES-----------------%()=νout+ = desired plusswingνout- = desired neg.swingνout- EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-3Typically output load is low impedance (but not always!)If it is, a source follower is a possible output stage.RLm3RREFIQVDDVINIQM2M1VOUT-VDDVDDRLVOUTVINIQ-VDDM3 M2M1Aνmax11 χ+------------≈EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-4VDDVDDVToVDSAT––VDD–IQRL⋅–VDDVINVDSATVDSATVGSVT–=VOUT MAX,VDDVT– VDSAT–=VOUT MIN,VDSATVDD–()+=⎧⎪⎪⎨⎪⎪⎩are the absolute maximum swings in the positive and negative directionsVout-, Vout+ are the desired positive and negative swings They typically should be equal for symmetric outputsEECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-512IQVout –RL--------------=RREFVDDVT– VDSAT–IQ------------------------------------VDDVT–IQ-------------------≈=VDSATVDDVOUT ––()=3WL-----⎝⎠⎛⎞22 IQ⋅k′-----------⎝⎠⎛⎞1VDDVOUT ––()2-------------------------------------⋅=Find the W/L of M1:IDS1IQIL+ IQVOUT 1+RL-------------+==To set WL-----⎝⎠⎛⎞2use Vout-EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-6k'2---WL-----⎝⎠⎛⎞1VDDVOUT 1+– VT–()2⋅⋅ IQVOUT 1+RL-------------+=4WL-----⎝⎠⎛⎞12 IQVOUT 1+RL-------------+⎝⎠⎛⎞⋅k' VDDVOUT 1+VT––()2⋅-----------------------------------------------------=e.g.VOUT 1+VOUT –3V==RL300Ω=IQ10ma=VDD5V=RREF30.7–10ma----------------230Ω==WL-----⎝⎠⎛⎞22102–×90 106–×---------------------153–()2------------------⋅ 56==WL-----⎝⎠⎛⎞122102–×()⋅90 106–53–0.7–()2⋅×---------------------------------------------------------263==EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-7GAINgmRLro||()⋅1 gmRLro||()⋅+--------------------------------------gmRL⋅1 gmRL⋅+------------------------≈=ROUT1gm-----RL||=gm2 k'WL-----IDS⋅⋅ ⋅⎝⎠⎛⎞12---290106–263 102–××××()12---22 103–×== =1gm-----45Ω=GAINRL1gm-----RL+-----------------30045 300+---------------------0.87== =ROUT1gm-----RL||45 300 40Ω≈||==EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-8Power VSUPPLYCurrentOut()⋅∑=Power@Vout = 0VDC Power without any SignalPower IM3–()VDD–()⋅ IM2–()VDD–()⋅ IM1()++VDD⋅=3 IQVDD⋅⋅=310103–×()5⋅⋅150mW==4 IQ⋅2 IQ⋅Average 3 IQ⋅=EfficiencyPower to Load3 IQVDD⋅⋅-----------------------------------%()=EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-9VOFFSETVINVOUT0V==VINVGS1VTO2 IDS⋅k'WL-----⋅-------------⎝⎠⎜⎟⎜⎟⎛⎞12---+0.7210103–××90 106–263××------------------------------------⎝⎠⎛⎞+1.6V== = =⎧⎪⎨⎪⎩V∆IQ=Efficiency (Sine Wave)VˆOV–OˆVOUTVˆOPeakVoltage=PL12---VˆOIˆO⋅⋅12---IQRL⋅()IQ⋅⋅12---IQ2RL⋅⋅== =12---104–300×⋅=15mW=EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-10VOUT 1––IQRLIM12IQIQ0IM1IQIRL+ IQVOUTRL---------+==VOUT 1–VOUT +=PSUPPLY1TC-----IDSm1()VDD⋅()td0TC∫⋅ 2 IQVDD⋅⋅+=⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩3 IQVDD⋅⋅=150mW=IQVDD⋅EfficiencyPLOADTotalPower-------------------------------15mW150mW-------------------10%===12---IQ2RL⋅⋅3 IQVDD⋅⋅------------------------⎝⎠⎜⎟⎜⎟⎛⎞=16---IQRL⋅VDD--------------⎝⎠⎛⎞⋅ 16<=%MAXEECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGESO-11OUTPUT STAGE - SOURCE FOLLOWER96 / 02 /18 12:03:262.99352.502.01.501.0500.0M0.-500.0M-1.0-1.50-2.0-2.50-3.0-5.0 -4.0 -2.0 0. 2.0 4.0 5.0VOLTS [LIN]VOLTLINSF.SW0VOUT∆VINVOUTEECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-12output stage - source follower****** reading file: /bobtools/commercial/hspice/hspice.ini*.model nch nmos level = 1 tox = 170 vto = 0.7 kp = 90.0e-6 lambda = 0.01+ gamma = 0.5 phi = 0.6 capop = 0 cgso=5.e-10 cgdo=5.e-10 cgbo=4.e-10 cj=1e-4.model pch pmos level = 1 tox = 170 vto = -0.7 kp = 30.0e-6 lambda = 0.01+ gamma = 0.5 phi = 0.6 capop = 0 cgso=3.e-11 cgdo=3.e-11 cgbo=4.e-10 cj=6e-4.option nopage post=2 absi = 1e-10 reli = 1e-4 absmos = 1e-8 relmos=1e-4+ absv=1e-6 relv=1e-4.options nomod*name drain gate source bulk modelm1 vdd vin vout vout nch l=1u w=263um2 vout d3 vdd- vdd- nch l=1u w=56um3 d3 d3 vdd- vdd- nch l=1u w=56urref 0 d3 230*iload vout vdd- 1marload 0 vout 300vin vin 0 1.6vdd vdd 0 5.0vdd- vdd- 0 -5.0.dc vin -5 5 .1 *sweep the input voltage.print dc i(m1) i(m2) i(m3) v(vout).op *initial operating point.tf v(vout,0) vin .measure tot_power avg power *makes it do the power calculation Small-signal transfer characterisitcs v(vout)/vin = 865.0433m input resistance at vin = 1.000e+20 output resistance at v(vout) = 38.2335EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-13Bipolar versionBipolar :VCC-++IQVCCM2M1RLVBE-VCESATVCC– IQRL⋅=VCCVBE–VCCVBE+ P-WELLEECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-14Bipolar (Cont.)VMAXVCCVBE– VMAX 1–==PL12---VCCVBE–()IQRL⋅⋅⋅=Efficiency12---VCCVBE–()IQRL⋅⋅⋅3 IQVCC⋅⋅----------------------------------------------------16---VCCVBE–()VCC-------------------------⋅==ICIS= e⋅VBEVThICIS----ln⋅ 0.06ICIS----log⋅==VBEVT-------for symmetry16---50.6–5----------------⎝⎠⎛⎞⋅=15%=EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-15More voltage range RL300Ω=VOUTVINM3M2M1RIQVDD–VDDInverter Output Stage :IQRL⋅VDD– VDSAT1+VDD0V+VDD–VDD– VT+VDD–VDDM1 LinearVDSAT2EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OUTPUT STAGES O-16IQVMAX 1+RL----------------3V300---------102–===VDSATVDDVMAX 1+–2 IQ⋅k'WL-----⋅-------------⎝⎠⎜⎟⎜⎟⎛⎞12---==1WL-----⎝⎠⎛⎞22 IQ⋅k'-----------1VDDVMAX
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