EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C. Nguyen PROBLEM SET #8 Issued: Tuesday, March 31, 2009 Due: Tuesday, April 7, 2009, 8:00 p.m. in the EE 140 homework box in 240 Cory 1. This problem concerns the class B output stage shown in Figure PS8-1(a). The input signal is()tfVvinmINπ2sin=. (a) If the load is resistive RZL= sketch timing diagrams of the output voltage()tvOUT, the load current()tiL, and collector currents ()tiC1and ()tiC2. (b) Repeat (a) if the load is capacitiveCjZLω1=. (c) The output stage is connected in a feedback loop as shown in Figure PS8-1(b). Sketch timing diagrams of()tvOUT,()tiL,()tiC1,()tiC2, and()tvA if RZL=. Assume amplifier A is ideal. (d) Repeat (c) ifCjZLω1=. Draw only one period in steady state. Clearly mark all important points in your diagrams. VVm9=,kHzfin1=,pFC 100=, Ω=500R , VVonBE7.0,=,VVVEECC10==. (a) (b) Figure PS8-1EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C. Nguyen 2. The slew rate of the circuit in Fig. PS8-2 is to be increased by using two 10 kΩ resistors placed at the emitters of Ql and Q2. If the same unity-gain frequency is to be achieved, calculate the new value of compensation capacitor required and the improvement in slew rate. RERE Figure PS8-1 3. Razavi, Chapter 9: Problem 9.19. 4. Razavi, Chapter 9: Problem
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