EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C Nguyen PROBLEM SET 8 Issued Tuesday March 31 2009 Due Tuesday April 7 2009 8 00 p m in the EE 140 homework box in 240 Cory 1 This problem concerns the class B output stage shown in Figure PS8 1 a The input signal is vIN Vm sin 2 fint a If the load is resistive Z L R sketch timing diagrams of the output voltage vOUT t the load current iL t and collector currents iC1 t and iC 2 t b Repeat a if the load is capacitive Z L 1 j C c The output stage is connected in a feedback loop as shown in Figure PS8 1 b Sketch timing diagrams of vOUT t iL t iC1 t iC 2 t and v A t if Z L R Assume amplifier A is ideal d Repeat c if Z L 1 j C Draw only one period in steady state Clearly mark all important points in your diagrams Vm 9V fin 1kHz C 100 pF R 500 VBE on 0 7V VCC VEE 10V a b Figure PS8 1 EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C Nguyen 2 The slew rate of the circuit in Fig PS8 2 is to be increased by using two 10 k resistors placed at the emitters of Ql and Q2 If the same unity gain frequency is to be achieved calculate the new value of compensation capacitor required and the improvement in slew rate RE RE Figure PS8 1 3 Razavi Chapter 9 Problem 9 19 4 Razavi Chapter 9 Problem 9 20
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