EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C. Nguyen PROBLEM SET #6 Issued: Tuesday, March 3, 2009 Due: Tuesday, March 10, 2009, 5:00 p.m. in the EE 140 homework box in 240 Cory 1. For the high-swing cascode mirror shown in Figure PS6-1 answer the following questions: (a) Calculate W such that the minimum output voltage for which both M1 and M2 are in satu-ration is 0.5V. Assume that M3-M5 can provide appropriate gate biases for M1 and M2. (b) Calculate W5 in order to achieve the minimum output voltage calculated in (a). (c) Briefly explain the function of M4. (d) What is the output resistance of this current source? (e) What is the change in IOUT for ΔVOUT=1V? (f) What is the resistance seen by the ideal current source IIN that biases M3 and M4? (g) Calculate input voltages VIN1 and VIN2. (h) Replace transistors M5 and M6 with one diode connected device. What is the W of the new device? 0,02.0,6.0,450,51,1001022=======−γλμμμμVVVVscmmfFCmLAIthnoxIN Figure PS6-1 2. Use half-circuit concepts to determine the differential-mode and common-mode gain of the circuit shown in Figure PS6-2. Neglect ro, ru and rb. Then calculate the differential-mode and common mode input resistance.EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C. Nguyen +VCC-VEEQ1Q2RLRCRCREvi1vi2vo1vo2 +VDD-VSSM1M2RDRDvi1vi2vo1vo2RtailItail Figure PS6-2 Figure PS6-3 3. Use half circuit analysis to determine (i) the differential-mode gain Adm, (ii) the common-mode gain Acm, (iii) the common-mode input to differential-mode output gain Acm-dm, and (iv) the differential-mode input to common-mode output gain Adm-cm for a resistively loaded differen-tial pair shown in Figure PS6-3 with mismatched resistive loads, R1 and R2. Assume that R1=10.1kΩ, R2=9.9kΩ, also assume ro1=ro2=∞, and Rtail=1MΩ. Use the following process parameters: tox=8 nm, μn=450 cm2/VS, Ld=0.09 μm, W=10um, L=1um. Then calculate the input offset voltage assuming a W/L mismatch of 2 percent besides the resistive load mismatch. Ignore the difference of the device threshold in your offset calculation. 4. This problem concerns the actively loaded MOS amplifier shown in Figure PS6-4. (a) Design the amplifier to achieve a differential small signal gain of 200. Bias M1 and M2 with 100μA of current each. The maximum output swing should be 2V peak-to-peak. Do not use overdrive voltages lower than 150mV. Choose W5 and W6 so that the bias currents of M5 and M6 are exactly the same at the quiescent point. Use the smallest channel lengths that satisfy the gain requirements. All transistors should have the same channel lengths. (b) If the desired output voltage at the quiescent point is in the middle of output signal range, what is the systematic input referred voltage offset of this amplifier? (c) Due to manufacturing imperfections threshold voltages, channel widths and channel lengths can differ from designed by ΔVth, ΔW, ΔL, where mVVth10<Δ, nmW 5<Δ, nmL 5<Δ. What is the worst case input referred voltage offset due to mismatches? 0,0,100,250,04.0,02.0,5.0,8.1,8.122,0,0==========−==doxpoxnSDdNDSdNpthnthSSDDLVACVACVmdVdXVmdVdXVVVVVVVγμμμμμαμαEE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C. Nguyen Figure
View Full Document
Unlocking...