EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C Nguyen PROBLEM SET 6 Issued Tuesday March 3 2009 Due Tuesday March 10 2009 5 00 p m in the EE 140 homework box in 240 Cory 1 For the high swing cascode mirror shown in Figure PS6 1 answer the following questions a Calculate W such that the minimum output voltage for which both M1 and M2 are in saturation is 0 5V Assume that M3 M5 can provide appropriate gate biases for M1 and M2 b Calculate W5 in order to achieve the minimum output voltage calculated in a c Briefly explain the function of M4 d What is the output resistance of this current source e What is the change in IOUT for VOUT 1V f What is the resistance seen by the ideal current source IIN that biases M3 and M4 g Calculate input voltages VIN1 and VIN2 h Replace transistors M5 and M6 with one diode connected device What is the W of the new device I IN 100 A L 1 m Cox 5 fF cm 2 450 Vth 0 0 6V 0 02V 1 0 n 2 m Vs Figure PS6 1 2 Use half circuit concepts to determine the differential mode and common mode gain of the circuit shown in Figure PS6 2 Neglect ro ru and rb Then calculate the differential mode and common mode input resistance EE 140 ANALOG INTEGRATED CIRCUITS VCC RC VDD RC RL RD RD vo1 vo2 vo1 vo2 vi1 Q1 SPRING 2009 C Nguyen Q2 vi2 RE vi1 M1 M2 Itail vi2 Rtail VSS VEE Figure PS6 2 Figure PS6 3 3 Use half circuit analysis to determine i the differential mode gain Adm ii the common mode gain Acm iii the common mode input to differential mode output gain Acm dm and iv the differential mode input to common mode output gain Adm cm for a resistively loaded differential pair shown in Figure PS6 3 with mismatched resistive loads R1 and R2 Assume that R1 10 1k R2 9 9k also assume ro1 ro2 and Rtail 1M Use the following process parameters tox 8 nm n 450 cm2 VS Ld 0 09 m W 10um L 1um Then calculate the input offset voltage assuming a W L mismatch of 2 percent besides the resistive load mismatch Ignore the difference of the device threshold in your offset calculation 4 This problem concerns the actively loaded MOS amplifier shown in Figure PS6 4 a Design the amplifier to achieve a differential small signal gain of 200 Bias M1 and M2 with 100 A of current each The maximum output swing should be 2V peak to peak Do not use overdrive voltages lower than 150mV Choose W5 and W6 so that the bias currents of M5 and M6 are exactly the same at the quiescent point Use the smallest channel lengths that satisfy the gain requirements All transistors should have the same channel lengths b If the desired output voltage at the quiescent point is in the middle of output signal range what is the systematic input referred voltage offset of this amplifier c Due to manufacturing imperfections threshold voltages channel widths and channel lengths can differ from designed by Vth W L where Vth 10mV W 5nm L 5nm What is the worst case input referred voltage offset due to mismatches VDD 1 8V VSS 1 8V Vth 0 n Vth 0 p 0 5V N nCox 250 A V 2 p Cox 100 A V2 0 Ld 0 dX d dX d m m 0 02 N 0 04 dVDS V dVSD V EE 140 ANALOG INTEGRATED CIRCUITS Figure PS6 4 SPRING 2009 C Nguyen
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