Report Guidelines Your project report should include the following sections Discussion of your topology choice explain why you chose a certain topology and compare your topology with possible alternatives Discussion of your bandwidth maximization strategy explain how you chose all the W s L s and currents show your calculations for important poles and zeros Discussion of your strategy to address variation of the supply voltage V DD A schematic of your circuit annotated with all the node voltages for both VDD min and VDD max on same schematic Provide a table with W L and the simulated value of Vdsat and Ids for every transistor For Ids include the simulated values for VDD VDD min and VDD VDD max Include simulated frequency characteristics curves of small signal differential and common mode voltage gain dB of your amplifier List 3dB bandwidth maximum in band common mode gain and the worst case total power consumption of your design and compare your calculations and the results from the test benches Comments and conclusion Note Assume that the power supplied by the 0 6V supply connected to RL is generated by VDD therefore the effective total current IDDT is equal to VDD IDD 0 6V IL VDD where IL is the current delivered to the load by the amplifier DO NOT INCLUDE SPICE NETLIST IN THE PROJECT REPORT Circuit submission guidelines Send an email to ee140 cory eecs berkeley edu with your name in the subject and your circuit in the body of the email Make sure to send the email in plain text not in html The body of the email should be the same as the file used to run the test bench param VIC your midpoint of the common mode input range subckt amplifier inp inn out vdd vss your circuit ends The subcircuit should be named amplifier and the order of the input nodes should be positive input node negative input node output node positive supply negative supply You can change the names of the nodes Transistor Capacitance Parameters LEVEL 2 ACM 3 GEO 0 AD AS 2 HDIF W AD AS area of drain area of source PD PS periphery of drain and source NOT including the gate width since the CJGATE model parameter separately models the drain and source periphery capacitances along the gate edge PD PS 4 HDIF W C0BD C0BS CJ AD C0BD SW C0BS SW CJSW PD CJGATE W LD lateral diffusion into channel from source and drain diffusion If CGD0 or CGS0 is not set then the gate drain or gate source overlap capacitance per meter channel width is calculated from LD and TOX you can assume fringing field factor is 0 i e no fringing CSUB bulk to substrate capacitance For this project we recommend you to connect bulk terminal of all NMOS and PMOS transistors to GROUND and VDD respectively Fig b You need to take into account CSUB in your analysis if bulk terminal of a transistor is not AC grounded for each individual transistor add its own CSUB Fig a You can assume that CSUB CSUB0 CJ ABulk Where ABulk the well area can be calculated as ABulk W 6um L 10um CSUB will be added to the transistor model sub circuits when we evaluate your design DO NOT use any capacitor in your netlist
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