UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R W Brodersen Sohrab Emami David Sobel Design Problem 2 Due 11 10 04 EECS 140 Fall 2004 You can work in groups of two or alone If you work in groups of two submit only one project report per group There will be no extra credit for working alone Information on what to include in the report and how to submit your circuit will be available later Design Objective The objective of this project is to design an operational amplifier Figure 1 with a differential input and a single ended output It must meet the following specifications Specification Lmin Wmin VDD min VDD max VSS RL Condition 0 13um 0 15um 1 2V 1 4V 0V 1k RS 500 ADM0 vout vid 1000 ACM0 vout vic 0 1 VICM max VICM min 0 3V Vout pp 0 6V Maximum supply current 3dB bandwidth of ADM f vout f vid f 1mA Maximize Notes L must be integer multiple of 0 01um W must be integer multiple of 0 01um Supply voltage VDD varies from VDD min to VDD max Don t include the load in your schematic It is automatically included in the testbenches Don t include the source resistance in your schematic It is included in the testbenches Low frequency small signal differential mode voltage gain Low frequency small signal common mode voltage gain ADM0 and ACM0 specs must be met over this common mode swing for both VDD min and VDD max VOUT 0 6V ADM0 spec must be met over this output swing for both VDD min and VDD max VICM Q i e VOUT must swing from 300mV to 900mv while maintaining ADM0 spec Maximum supply current over the entire range of Vout and VDD At Vout 0 6V VDD 1 2V and VICM VICM Q Also ACM f must remain less than 0 1 over this bandwidth And the design goal is to maximize the 3dB bandwidth of the differential to singleended voltage gain of the amplifier The available circuit components are NMOS transistors PMOS transistors and resistors Ideal internal sources can not be used to generate bias currents or voltages Figure 1 Device Models http bwrc eecs berkeley edu classes ee140 dp model ee140 sp The device models are encapsulated in a sub circuit use x1 d g s b nmos w 10u l 0 13u x2 d g s b pmos w 10u l 0 13u to instantiate an NMOS and a PMOS transistor respectively you have to use the prefix x instead of m The reason for using a subcircuit is to allow to decrease with increasing transistor length The output resistance parameter will stay the same as before for minimum length transistors Lmin 0 13 m but will decrease with increasing L drawn L not effective L Since the output resistance is proportional to 1 the output resistance increases with increasing L Spice testbenches Test benches will be provided for you to run a set of simulation tests on your circuit Ultimately your final circuit performance will be evaluated by these testbenches More information on the testbenches and the testbenches themselves will be released in another document on the website Please note that the testbench files will include all your input sources power signal as well as your source and output resistances Therefore you do NOT need to include these devices in your own netlist What to include in your report See handout on webpage Grading 100 points total 25 points for conciseness and clearness of the report 40 points for meeting the specifications 25 points for how well the 3 dB bandwidth is maximized 10 points for originality of the design
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