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Berkeley ELENG 140 - Design Problem 2

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UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R. W. Brodersen Design Problem 2 EECS 140 Sohrab Emami (Due 11/10/04) Fall 2004 David Sobel You can work in groups of two, or alone. If you work in groups of two, submit only one project report per group. There will be no extra credit for working alone. Information on what to include in the report and how to submit your circuit will be available later. Design Objective The objective of this project is to design an operational amplifier (Figure 1) with a differential input and a single-ended output. It must meet the following specifications: Specification Condition Notes Lmin 0.13um L must be integer multiple of 0.01um Wmin 0.15um W must be integer multiple of 0.01um VDD-min 1.2V VDD-max 1.4V Supply voltage, VDD, varies from VDD-min to VDD-max. VSS 0V RL 1kΩ Don’t include the load in your schematic. It is automatically included in the testbenches RS 500Ω Don’t include the source resistance in your schematic. It is included in the testbenches ADM0 (=vout/vid) ≥1000 Low frequency small-signal differential-mode voltage gain ACM0 (=vout/vic) ≤0.1 Low frequency small-signal common-mode voltage gain VICM,max - VICM,min ≥0.3V ADM0 and ACM0 specs must be met over this common-mode swing for both VDD-min and VDD-max @ VOUT=0.6V Vout,pp ≥0.6V ADM0 spec must be met over this output swing for both VDD-min and VDD-max @ VICM,Q. (i.e. VOUT must swing from 300mV to 900mv while maintaining ADM0 spec.) Maximum supply current 1mA Maximum supply current over the entire range of Vout and VDD. 3dB-bandwidth of ADM(f) (=vout(f)/vid(f)) Maximize At Vout=0.6V, VDD=1.2V, and VICM=VICM,Q. Also |ACM(f)| must remain less than 0.1 over this bandwidth. And the design goal is to maximize the 3dB-bandwidth of the differential to single-ended voltage gain of the amplifier.The available circuit components are NMOS transistors, PMOS transistors, and resistors. (Ideal internal sources can not be used to generate bias currents or voltages.) Figure 1 Device Models http://bwrc.eecs.berkeley.edu/classes/ee140/dp/model_ee140.sp The device models are encapsulated in a sub-circuit; use: x1 d g s b nmos w=10u l=0.13u x2 d g s b pmos w=10u l=0.13u to instantiate an NMOS and a PMOS transistor respectively (you have to use the prefix ‘x’ instead of ‘m’). The reason for using a subcircuit is to allow λ to decrease with increasing transistor length. The output resistance parameter λ will stay the same as before for minimum length transistors (Lmin=0.13µm), but will decrease with increasing L (drawn L, not effective L). Since the output resistance is proportional to 1/ λ, the output resistance increases with increasing L. Spice testbenches Test benches will be provided for you to run a set of simulation tests on your circuit. Ultimately, your final circuit performance will be evaluated by these testbenches. More information on the testbenches (and the testbenches themselves) will be released in another document on the website. Please note that the testbench files will include all your input sources (power, signal) as well as your source and output resistances. Therefore, you do NOT need to include these devices in your own netlist. What to include in your report See handout on webpageGrading 100 points total: 25 points for conciseness and clearness of the report 40 points for meeting the specifications 25 points for how well the 3-dB bandwidth is maximized. 10 points for originality of the


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