UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R. W. Brodersen, Homework #2 EECS140 S. Emami, and D. Sobel (Due 9/15/04) Fall 2004 1. Consider the structure shown in Figure 1. This two-transistor structure can be considered a new type of single device (the “Cal-sistor”) with the drain, source, and gate nodes as given. For this problem, assume that λ=γ=0. M1W/LM2VDSIDSVGSW/L Figure 1 a) Determine the VDS and VGS conditions for each of the 3 operating modes (cutoff, saturation, and linear) for the Cal-sistor. b) Determine IDS as a function of VGS and VDS for each of these 3 modes. G S D2. For each of the two circuits in figure 2, perform the calculations for (a) and (b) by hand. Assume VT0=0.5V, k’W/L = 8mA/V2, λ=0.1V-1, γ=0.2V1/2, R1=10kohm, R2=2kohm, R3=10kohm, R4=10kohm, VDD=3V. VINVOUTVDDR1R2VINVOUTVDDR4R3 Figure 2 a) Determine the dc voltage VIN so that VOUT is at 1.5V. Assume that VIN is between 0 and VDD. b) Calculate the operating point parameters IDS, VT and VDSAT, and the small signal-paramters gm, gmbs, and ro. 3. Razavi, problem 2.5, parts a-d. Some notes on the problems are below a. Table 2-1 w/ the required device parameters is on p. 37 b. Be sure to numerically label the voltages breakpoints at which the transistor changes modes (i.e. from linear to saturation and so forth). c. Remember that the notation for a drain vs. source node is only notation! For an NMOS device, the drain is determined by which of these two nodes has a higher voltage. Therefore, as voltages are swept, the drain and source nodes can become
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