UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R. W. Brodersen Project 1 EECS 140 Jianhui Zhang (Due 11/05/03) Fall 2003 This is an individual project. Everybody should turn in a project report. 1. Design Objective The objective of this project is to design an operational amplifier having a differential input and a single ended output and with the following specifications: Process 0.13um VDD 1.2V Adm ≥10000 Acm ≤ 0.02 RLOAD 50Ω VICM,max – VICM,min ≥0.4V VID ≤ 100uV Vout,pp ≥ 0.8V VDsat ≥ 100mV Total Power dissipation Minimize Area MinimizeYou are free to choose the midpoint of the common mode input range. The requirement of VID ≤ 100uV means that differential mode offset voltage is less than 100uV. For a differential offset input and a common mode input at the midpoint of the common mode input range, the output should be 0 V under nominal supply conditions. Your circuit should only use the positive +VDD/2 and the negative -VDD/2 supply. The design specifications should be met under a variation of the supply voltages of 10 % (higher or lower than the nominal voltage). The available components are: NMOS transistors, PMOS transistors and resistors. Ideal sources can only be used to generate the supply voltages, not to generate bias currents. Area Calculation Calculate the area by adding up the gate area (W*L) of all the transistors and the area of the resistors. For the transistors, the minimum L is 0.13 µm and the minimum W is 0.25 µm. For the resistors, the minimum W and L are 0.5 µm ; the sheet resistance is 250Ω/square. You are allowed to tie the bulk of any transistor to the source instead of to the positive or negative supply, but at the cost of an area penalty. If you choose to tie the bulk to the source, the area of the transistor should be doubled. Device Models http://bwrc.eecs.berkeley.edu/classes/ee140/projects/proj1_model.sp The device models are encapsulated in a sub-circuit; use: x1 d g s b nmos w=10u l=0.13u x2 d g s b pmos w=10u l=0.13u to instantiate an NMOS and a PMOS transistor respectively (you have to use the prefix ‘x’ instead of ‘m’). The reason for using a subcircuit is to allow λ to decrease with increasing transistor length. The output resistance parameter λ will stay the same as before for minimum length transistors (Lmin=0.13µm), but will decrease with increasing L (drawn L, not effective L). Since the output resistance is proportional to 1/ λ, the output resistance increases with increasing L. Grading 100 points total: 20 points for conciseness and clearness of the report 20 points for meeting the specifications 20 points for how well the total power dissipation is minimized 20 points for how well the area is minimized 20 points for originality of the
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