UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R W Brodersen Mike Chen Design Problem 3 Due 4 20 04 EECS 140 Spring 2004 1 Design Specification You are asked to design a wideband gain amplifier that drives a sample and hold circuit modeled as a 50 resistor in series with 2 pF sampling capacitor shown in Figure 1 The available circuit components are NMOS transistors PMOS transistors or resistors Ideal sources can only be used to generate the supply voltages not to generate bias currents or voltages The design specifications are as following Lmin 0 13 m Wmin nmos 0 15 m Wmin pmos 0 15 m W and L has to be integer multiple of 0 01 m Vdd 1 2 V Vss 0 V Input common mode voltage swings 0 5V with less than 10 Adm variation You are free to choose the midpoint of input common mode range Output peak peak voltage swings 0 4V with less than 10 Adm variation You are free to choose the midpoint of input common mode range You can apply input offset voltage 1mV within your circuit sp Adm Total differential mode gain Vout Vid 1 000 Acm Total common mode gain Vout Vic 0 1 Area 500 m2 3dB bandwidth 300 MHz The design goal is to Maximize the 3 dB bandwidth Minimize the power consumption Watts Vdd 500 ohms Vi1 50 ohms Vout Vi2 500 ohms 2 pF Vss Figure 1 2 Area Calculation Calculate the area by adding up the gate area W L of all the transistors and the area of the resistors For the transistors the minimum L is 0 13 m and the minimum W is 0 15 m For the resistors the minimum W and L are 0 5 m the sheet resistance is 2501 square You are allowed to tie the bulk of any transistor to the source instead of to the positive or negative supply but at the cost of an area penalty If you choose to tie the bulk to the source the area of the transistor should be doubled 3 Device Models http bwrc eecs berkeley edu classes ee140 dp model ee140 sp The device models are encapsulated in a sub circuit use x1 d g s b nmos w 10u l 0 13u x2 d g s b pmos w 10u l 0 13u to instantiate an NMOS and a PMOS transistor respectively you have to use the prefix x instead of m The reason for using a subcircuit is to allow 2 to decrease with increasing transistor length The output resistance parameter 2 will stay the same as before for minimum length transistors Lmin 0 13 m but will decrease with increasing L drawn L not effective L Since the output resistance is proportional to 1 2 the output resistance increases with increasing L Since we are using level 2 device model it is worthwhile to calculate level 1 parameters of the device model for your hand calculations Ref problem 1 of HW1 extracting K 2 etc A transistor characterization tool called tchar is kindly provided by Ian O Donnell You can run from your UNIX account perl home ff ee140 tchar tchar140 pl For this design problem only look at the model with proc TT and temp 25 4 Run testbench Perform dc operation point AC and small signal transfer function analysis Testbench 1 1 Operating point and differential mode gain for your chosen VIC VOC Purpose check specs for Adm Psupply VDsat 2 Operating point and differential mode gain for VIC midpoint 0 25 V Purpose check common mode range Adm may vary up to 10 from the value at the midpoint of the common mode range 3 Operating point and differential mode gain for VIC midpoint 0 25 V Purpose check common mode range Adm may vary up to 10 from the value at the midpoint of the common mode range 4 Common mode gain for VIC midpoint Purpose check Acm 5 AC analysis on 3 dB frequency for all situations Testbench 2 1 AC analysis differential mode gain at 1 Hz for VOUT VOC V 2 AC analysis differential mode gain at 1 Hz for VOUT VOC 0 2 V Purpose check output range Adm may vary up to 10 from the value for VOUT VOC V 3 AC analysis differential mode gain at 1 Hz for VOUT VOC 0 2 V Purpose check output range Adm may vary up to 10 from the value for VOUT VOC V Usage put testbench1 dp3 sp testbench2 dp3 sp model ee140 sp circuit sp in the same directory and run hspice testbench1 dp3 sp o testbench1 dp3 and hspice testbench2 dp3 sp o testbench2 dp3 5 What to include in your report http bwrc eecs berkeley edu classes ee140 dp guidelines dp3 pdf 6 Grading 100 points total 45 points for conciseness and clearness of the report 35 points for meeting the specifications 20 points for how well you optimize the goals
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