UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R W Brodersen S Emami and D Sobel Homework 4 Due 10 13 04 EECS140 Fall 2004 1 For the circuit above assume all wells are tied to their respective sources VDD 1 8 V Lmin 0 18 m Vin is referenced to ground a Choose RREF and the W Ls so that the output ranges from 1 0 to 1 0 volts with the highest efficiency and smallest area All devices should be in saturation over the range of operation You may choose your own value for the DC level at the input b Plot Vout vs Vin for 1 8 Vin 1 8 V to demonstrate the output range c Calculate the sine wave efficiency power into load total power for a sine wave output with an amplitude of 1 V d Check the efficiency with SPICE Use the following NMOS and PMOS transistor models for all parts of the homework model nch nmos LEVEL 1 TOX 2 5n VTO 0 5 KP 140 0e 6 LAMBDA 0 1 GAMMA 0 5 PHI 0 6 model pch pmos LEVEL 1 TOX 2 5n VTO 0 5 KP 65 0e 6 LAMBDA 0 15 GAMMA 0 5 PHI 0 6 2 For the circuit above assume all wells are tied to their respective sources VDD 1 8 V Use the same device models as in P 1 Lmin 0 18 m Vin is referenced to the negative supply rail a Choose RREF such that the bias current through M2 M5 is 1 A b Choose the W Ls of M6 and M7 so that the output ranges from 1 0 to 1 0 volts with the highest efficiency and smallest area All devices should be in saturation over the range of operation You may choose your own value for the DC level at the input c Plot Vout vs Vin only in the high gain region to demonstrate the output range d Calculate the sine wave efficiency power into load total power for a sine wave output with an amplitude of 1 V e Check the efficiency with SPICE VDD M3 M4 2 0 18 2 0 18 M5 M6 2 0 18 2 0 18 1 A Rout Vout M7 1 0 18 M8 1 0 18 M9 Vi1 1 10 M1 5 0 18 Vi2 5 0 18 Vid 2 Vic M2 RREF Vid 2 M10 M11 21 2 10 2 VSS VSS 3 Do the following for the circuit above Assume that the wells of all NMOS transistors are tied to the sources of those devices while all PMOS transistors have their bulk terminals tied to VDD Assume dual supplies of VDD 1 8 V and VSS 1 8 V Use the same device models as in P 1 a Choose RREF so that the IDS of M1 M8 is 10 A when VIC 0 V b Use SPICE to plot Vout vs Vid with VIC 0 over the range 10 mV Vid 10 mV Explain what causes the breakpoints in the graph and calculate the values of Vout at the breakpoints by hand Hint there are four breakpoints c Use SPICE to plot Vout vs Vic with VID 0 over the range 1 8 Vic 1 8 V Explain what causes the breakpoints in the graph and calculate the values of Vic at the breakpoints by hand Hint there are three breakpoints d Calculate Adm vout vin with VIC VID 0 e Calculate Rout with VIC VID 0 Verify d and e with SPICE using the TF analysis option and explain any differences greater than 10 Hint How to verify the efficiency with HSPICE i Make your input voltage source a sine wave source vin in1 in2 sin dc voltage amplitude freq ii Do a transient analysis time domain analysis for one period of the sine wave ex f 1kHz and measure the power into the load and the total supply power meas meas meas meas meas tran tran p load avg p rload tran p supply p avg p vddp tran p supply n avg p vddn tran p supply param p supply p p supply n tran p eff param 100 p load p supply 1u 1m where rload is the load resistance vddp is the positive supply and vddn is the negative supply The measured values will be listed in your output file p eff is the efficiency
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