EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS OP 1 Miller Op Amp University of California Berkeley VDD College of Engineering Department of Electrical Engineering and Computer Science M3 Robert W Brodersen V d1 EECS140 V d2 Vd1 Analog Circuit Design M4 Vd2 M5 OUT v1 1 Lectures on OP AMPS 2 v2 M1 M2 M13 Rc Vdd EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS OP 2 Miller Op Amp Cont OUT 1 2 OUT i d R OUT a id M12 M6 Vdd Vdd EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS Miller Op Amp Cont What is the DC voltage at Vd2 I DS 1 I DS 2 I DS 3 I DS4 k W 2 I DS 3 V SG3 VT 1 V SD3 2 L k W I DS 4 V SG4 VT 2 1 V SD4 2 L I DS 3 I DS 4 R id OUT d2 OUT id id d2 R O U T r o5 r o6 V SG3 VT 1 V SD3 V SG4 V T 1 V SD4 2 2 V SG3 V SG4 g m2 r o2 r o4 g m5 ROUT V SG3 V T 1 VSD3 VSG3 V T 1 VSD 4 2 2 V SD3 V SD4 VSG 3 V T VD S A T3 V D1 V DD V SG3 V DD V T V D S A T 3 V D2 OP 3 EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS OP 4 Miller Op Amp Cont To set offset at output or 2nd stage M5 M6 to near zero set IDS5 I DS6 What happens if I 1 I 2 k W 2 I SD5 VSG 5 V T 1 V SD5 2 L 5 I DS5 I DS6 k W V SG1 VT 2 1 V SD1 2 L 1 k W 2 I SD6 VGS 6 V T 1 V DS6 2 L 6 1 I SD6 I SD13 2 then I DS6 I DS5 W L W L 3 W W 2 L L 13 6 if if k W 2 V SG2 V T 1 V SD 2 2 L 2 M2 M1 Since VSD 4 V SG3 V SG5 I SD5 I DS3 1 V SD1 1 V SD2 I1 5 I2 V SD2 or 0 01 LECTURES ON OP AMPS Miller Op Amp Cont 1 V SD1 1 1 1 2 W W W 2 L L L I DS 5 5 6 6 I DS 3 W W W 2 L L L 3 13 13 EECS140 ANALOG CIRCUIT DESIGN V SD2 V SD1 100 VSD 1 V SD2 100 1 2 100 2 V SD1 Big Offset EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS OP 6 Miller Op Amp Cont Gain First Stage ds g m 1 r o4 r o2 id Second Stage OUT g m5 r o6 r o5 d2 Overall A g m1 g m5 r o4 r o2 r o5 r o6 OP 5 Miller Op Amp Cont 2 I D S1 2 I DS5 1 1 A VD S A T 1 V D S A T 5 n p I DS1 n p I DS 5 4 2 VD S A T 1 V D S A T5 n p 4 A 1 12 2 I 2 I DS 5 2 SD 1 n p 2 k n W L 1 k P W L 5 1 1 1 2 W 2 W 2 2 k n k P L L 1 5 1 n p 2 I SD1 I DS 5 2 OP 7 EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS Miller Op Amp Cont EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS OP 8 1 R O U T r o5 r o6 p n I DS5 OP 9 Miller Op Amp Cont You need to choose an operating point since the Rout is very non linear Add output stage if this is too high 1 R OUT g m1 M1 V OUT V IN M2 What is the output resistance of this V I N V Tn 1 g m2 VIN VT p 1 1 2 2 W W g m 2 k I DS 2 k I OUT L L RL 1 W VOUT 2 2 k L RL EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS h OP 10 Empty Slide OP 11 You could use a level shifter VDD 4V 4V W L 1 4 V 4 V V DD 5V id dc offset V id How to connect these EECS140 ANALOG CIRCUIT DESIGN OP1 SW0 VOUT2 LECTURES ON OP AMPS VOUT1 OP 12 DIFF PAIR GATE VOLTAGE SWEEP 96 10 03 18 13 44 EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS Area Calculation L 5 micron minimum channel Length OP 13 4 50 W L 3 W 4 0 3 50 3 0 Resistor Area of squares 1 0 2 2 50 2 0 V O L T 1 50 1 0 500 0M 0 500 0M L 1 0 L I N Resistor W L 1 2 T r a n s i s t o r A r e a 1 5 0 5 1 2 25 2 1 0 1 50 2 0 2 50 3 0 3 50 4 0 0 5 4 50 5 0 10 0M 5 0M 0 5 0M VOLTS LIN 0 5 10 0M EECS140 ANALOG CIRCUIT DESIGN LECTURES ON OP AMPS EECS140 ANALOG CIRCUIT DESIGN OP 14 Sheet Resistance LECTURES ON OP AMPS Sheet Resistance Cont TOP VIEW count as 1 2 square 1 L 1 W T Conductance Resis tan c e L L R b l W ohms 1 T 1 1 1 1 5 1 W W 1 W 1 1 1 1 1 1 1 15 W T mhos cm 3 15 SQUARES R 15 b l 1 100 1 R 1 5 k OP 15
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