UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R W Brodersen S Emami and D Sobel Homework 7 Due 11 24 04 EECS140 Fall 2004 1 For the operational amplifier shown below a Calculate the open loop differential mode voltage gain b Calculate the unity gain bandwidth c Calculate the slew rate d Compare your results of a c with HSPICE simulation results Comment on the phase characteristics and close loop stability of the amplifier Assume that the gate of M 9 is connected to the positive power supply its bulk is tied to the negative power supply and the W L of M 9 has been chosen to cancel the right half plane zero Bulk terminal of all other transistors are connected to their respective source terminal The Input sources have no dc voltage VIC 0 V and referred to the ground Use the following SPICE models For any unspecified parameters use the default values from HSPICE Assume the lambda for layout rules is 0 09 m and include the area and perimeter information for all transistors model nch nmos level 1 tox 2 5n vto 0 5 kp 140e 6 lambda 0 1 gamma 0 5 phi 0 6 capop 0 cgso 5e 10 cgdo 5e 10 cgbo 4e 10 cj 6e 4 cjsw 2e 10 model pch pmos level 1 tox 2 5n vto 0 5 kp 65e 6 lambda 0 15 gamma 0 5 phi 0 6 capop 0 cgso 5e 10 cgdo 5e 10 cgbo 4e 10 cj 6e 4 cjsw 2e 10 2 If the circuit below is used to generate the voltage to be applied to the gate of transistor M 9 of the operational amplifier of problem 1 calculate the W L of M 9 required to move the righthalf plane zero to infinity Compare your results with HSPICE simulation results Use the SPICE models of P 1 and tie the bulk of transistor M11 to the negative power supply 3 Razavi 8 18 page 288 4 Razavi 8 19 page 288
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