5.4: A 5GHz CMOS Transceiverfor IEEE 802.11a Wireless LANDavid Su, Masoud Zargari, Patrick Yue,Shahriar Rabii, David Weber, Brian Kaczynski,Srenik Mehta, Kalwant Singh, Sunetra Mendis,and Bruce Wooley1Atheros Communications, Sunnyvale, California1Stanford University, Stanford, CaliforniaOutline❑ Introduction: 802.11a Wireless LAN❑ Architecture❑ Radio Design• Transmitter• Receiver• Frequency Synthesizer❑ SummaryIEEE 802.11a WLAN■ Frequency: 5 GHz UNII (Unlicensed NationalInformation Infrastructure)■ Total UNII Bandwidth: 300 MHz (> IEEE 802.11b)■ Modulation: OFDM(Orthogonal Frequency Division Multiplexing)+ BPSK / QPSK / 16QAM / 64QAM■ Data Rate: 6 - 54 Mbps5.15G 5.25G 5.35G5.725G 5.825G40mW200mW800mWSpectral-Efficient Modulation■ 64-QAM (Quadrature Amplitude Modulation)— Large signal to noise ratio > 30dB• Phase noise• I/Q mismatch■OFDM (Orthogonal Frequency Division Mux)— Large peak to average power ratio of or17dB• TX: large power backoff• RX: large dynamic range• Some signal clipping can be tolerated Requires High Linearity52ArchitectureArchitecture + –DirectConversion- No off-chip IF filter- Single synthesizer- LO leakage- LO pulling- Quadrature LORF- DC offsetTraditionalSuperheterodyne- Low LO leakage- Weak LO pulling- No quadrature LO- Design flexibility- Off-chip IF filter- Two synthesizersDual conversion with 1GHz sliding IFRadio TransceiverRx_outSynthesizerControl5GHzReceiverTx_inTransmitterDual Transmit Conversion■ Radio Frequency (RF) ≠ Local Oscillator (LO)• LO leakage is out of band• LO pulling by power amplifier is reduced■Sliding Intermediate Frequency (IF):• Single synthesizer• Excellent 1 GHz quadrature for good transmit imagerejection■Double Image-reject mixers• Avoid IF filtering of sidebandLOIFLORF4---------------=Freq(Hz)LORF1G 5G4GdcLOIFTransmitter Block DiagramRF_OUTLOIF(I)PALORF(I)LORF(Q)LOIF(Q)LOIF(I)TX_ITX_Q5 GHzDual Receive Conversion■ No external IF filtering■ Channel selection at Baseband with passiveLC filtering■ Very high IF of 1GHz• 3GHz image is 2GHz away from 5GHz signal• Inherent bandpass filtering of 3GHz: –23dBc• RF mixer: 5-4 = 1GHz (IF) and 5+4 = 9GHz• No image-reject mixersFreq(Hz)fRFfIF1G 3G 5G4GdcLORFLOIFLNALOIF (Q)PGADACDACRF_INRX_IRX_QOffsetPGAoff-chipControlReceiver Block Diagram5GHzLC LPFoff-chipLC LPFLORFLOIF (I)Synthesizer■ Single synthesizer with sliding IF:■ Divide-by-four generates quadrature LOIF• Excellent I/Q matching■P+/N-well varactor■ Frequency Plan:LOIFLORF4---------------=RF 5.160 to 5.340 GHz 10 MHz spacingLORF4.128 to 4.272 GHz 8 MHz spacingLOIF1.032 to 1.068 GHz 2 MHz spacingSynthesizer Block DiagramLOIFLORFPFDCPVCORC LPF8MHz3216/17Decoder(4GHz)(1GHz)Channel Select4off-chip5GHz CMOS RF Design■ Advantages:• Low-cost, high-yield• Multi-layer interconnect makes decent inductors• High-level of integration supports sophisticateddigital signal processing*■Challenges:• 5 GHz: 0.25µm + narrowband with inductors• No high-Q BPF: architecture + dynamic range• Process/Temp Variation: DSP algorithms• Noise/Power performance limitations* J. Thomson et al, ISSCC 2002, Paper 7.2Power Amplifier Design■ Large peak to average ratio (PAR) of or 17dB■ Signal peaks are infrequent: 0.25dB SNRdegradation when PAR reduced to 6dB for16-QAM*.■ Implications:• Poor power efficiency• With 6dB PAR, to obtain 40mW (16dBm) requiresPsat of ~22dBm or 160mW• With 17dB PAR, to obtain 40mW (16dBm) requiresPsat of ~33dBm or 2W*Van Nee & Prasad, OFDM for Wireless Multimedia Communications,Artech House, 200052Power Amplifier TopologyOutputBiasL3InputL2*M2M3C2L4*Vpa = 3.3V■ Class A operation■ Cascoded• 3.3V supply voltage• Stability■Capacitive Level-shift• Metal-2,3,4,5 stacks■Inductive loads■ Differential• Off-chip balun* C.P. Yue and S.S. Wong, IEEE JSSC, May 1998Power Amplifier SchematicVin+Vin-Vpa=3.3VL1pC1pVout+BiasL3pBiasL2pM2pM3pC2pL4pL1nC1nVout-BiasL3nBiasL2nM2nM3nC2nL4nPSAT= 22 dBmMeasured BPSK OFDM Spectrum16.25MHzPOFDM = 17.8 dBm64QAM (300kHz) modulated signalMeasured Transmit ConstellationMeasured Transmit Output Power6 9 12 18 24 36 48 5412141618OFDM Output Power (dBm)Data Rate (Mbps)10Carrier Leak –29dBcSpectral Images –51dBcLNA SchematicReceiver NF: LNA to Baseband = 8dBVin+VoutM3M1Vin-M4M2Lsp LsnVddVin+ Vin-Vout- Vout+Vos+ Vos-offset controlR1R2R2VddBias_pBias_nBias_nProgrammable Baseband AmplifierVddMeasured Receiver Performance-30-90 -80 -70 -60 -50 -40 -20 -10 0-60-50-40-30-20-10010Min. GainMax. GainRF Input (dBm)IF Mixer Output (dBm)M1M2VcControlVoltage Controlled Oscillator (VCO)ControlFrequency (Hz)Phase Noise (dBc/Hz)1k 10k 100k 1M 10M–130–120–110–100–90Composite Phase Noise at 5GHz–80Die PhotographTxRxSynthBiasLogicMeasured PerformanceTX Output Power Level 22 dBmRX Chain Noise Figure 8 dBPhase Noise (∆f=1MHz) –112 dBc/HzSupply Voltages 2.5 V & 3.3 V I/OTX Chain Power Dissipation 790 mWRX Chain Power Dissipation 250 mWSynthesizer Power Dissipation 180 mWTechnology 0.25 µm 1P5M CMOSPackage 64-pin LPCCDie Size22 mm2Conclusions■ IEEE 802.11a radio transceiver in 0.25 µmstandard digital CMOS for 5-GHz WLAN■ No external IF filter:• TX: double image-reject mixers• RX: very high IF of 1GHz■Dual conversion with sliding IF: singlesynthesizer■ Integration of:• transmitter with 22dBm output power• receiver with 8dB noise figure• synthesizer with –112dBc/Hz (∆f=1MHz)Acknowledgement■ Support of the Wireless Team at Atheros fordesign, layout, and testing. In particular:H. Dieh, J. Kung, R. Popescu, A. Ong,J. Zheng, D. Nakahira, R. Subramanian,J. Kuskin, A. Dao, D. Johnson, C. Lee, L. Thon,P. Husted, W. McFarland, S. Wong, R. Bahr, T.Meng■ Assistance of TSMC. In particular: S. C. Wongand B. K.
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