5 4 A 5GHz CMOS Transceiver for IEEE 802 11a Wireless LAN David Su Masoud Zargari Patrick Yue Shahriar Rabii David Weber Brian Kaczynski Srenik Mehta Kalwant Singh Sunetra Mendis and Bruce Wooley1 Atheros Communications Sunnyvale California 1Stanford University Stanford California Outline Introduction 802 11a Wireless LAN Architecture Radio Design Transmitter Receiver Frequency Synthesizer Summary IEEE 802 11a WLAN Frequency 5 GHz UNII Unlicensed National Information Infrastructure 40mW 5 15G 800mW 200mW 5 25G 5 35G 5 725G 5 825G Total UNII Bandwidth 300 MHz IEEE 802 11b Modulation OFDM Orthogonal Frequency Division Multiplexing BPSK QPSK 16QAM 64QAM Data Rate 6 54 Mbps Spectral Ef cient Modulation 64 QAM Quadrature Amplitude Modulation Large signal to noise ratio 30dB Phase noise I Q mismatch OFDM Orthogonal Frequency Division Mux Large peak to average power ratio of 52 or 17dB TX large power backoff RX large dynamic range Some signal clipping can be tolerated Requires High Linearity Architecture Architecture Direct Conversion No off chip IF filter LO leakage Single synthesizer LO pulling Quadrature LORF DC offset Traditional Low LO leakage Off chip IF filter Superheterodyne Weak LO pulling Two synthesizers No quadrature LO Design flexibility Dual conversion with 1GHz sliding IF Radio Transceiver Transmitter 5GHz Synthesizer Tx in Control Rx out Receiver Dual Transmit Conversion dc 1G LOIF 4G 5G LORF Freq Hz Radio Frequency RF Local Oscillator LO LO leakage is out of band LO pulling by power ampli er is reduced LO RF 4 Sliding Intermediate Frequency IF LO IF Single synthesizer Excellent 1 GHz quadrature for good transmit image rejection Double Image reject mixers Avoid IF ltering of sideband Transmitter Block Diagram LORF I LOIF I TX I PA RF OUT 5 GHz LOIF Q TX Q LORF Q LOIF I Dual Receive Conversion fRF fIF dc 1G LOIF 3G 4G LORF 5G Freq Hz No external IF ltering Channel selection at Baseband with passive LC ltering Very high IF of 1GHz 3GHz image is 2GHz away from 5GHz signal Inherent bandpass ltering of 3GHz 23dBc RF mixer 5 4 1GHz IF and 5 4 9GHz No image reject mixers Receiver Block Diagram LORF LOIF I PGA off chip LC LPF LNA RX I DAC RF IN 5GHz DAC off chip LC LPF RX Q PGA LOIF Q Offset Control Synthesizer Single synthesizer with sliding IF LO RF LO IF 4 Divide by four generates quadrature LOIF Excellent I Q matching P N well varactor Frequency Plan RF 5 160 to 5 340 GHz 10 MHz spacing LORF 4 128 to 4 272 GHz 8 MHz spacing LOIF 1 032 to 1 068 GHz 2 MHz spacing Synthesizer Block Diagram 8MHz PFD CP 32 off chip RC LPF VCO LORF 4GHz 16 17 Decoder Channel Select 4 LOIF 1GHz 5GHz CMOS RF Design Advantages Low cost high yield Multi layer interconnect makes decent inductors High level of integration supports sophisticated digital signal processing Challenges 5 GHz 0 25 m narrowband with inductors No high Q BPF architecture dynamic range Process Temp Variation DSP algorithms Noise Power performance limitations J Thomson et al ISSCC 2002 Paper 7 2 Power Ampli er Design Large peak to average ratio PAR of 52 or 17dB Signal peaks are infrequent 0 25dB SNR degradation when PAR reduced to 6dB for 16 QAM Implications Poor power ef ciency With 6dB PAR to obtain 40mW 16dBm requires Psat of 22dBm or 160mW With 17dB PAR to obtain 40mW 16dBm requires Psat of 33dBm or 2W Van Nee Prasad OFDM for Wireless Multimedia Communications Artech House 2000 Power Ampli er Topology Vpa 3 3V L2 L3 C2 Class A operation Cascoded 3 3V supply voltage Output Stability Capacitive Level shift Metal 2 3 4 5 stacks Input M2 M3 L4 Inductive loads Differential Off chip balun Bias C P Yue and S S Wong IEEE JSSC May 1998 Power Ampli er Schematic Vpa 3 3V L2p L3p Vout M3p C2p L1p L1n C1p C1n L3n L2n C2n M2p M2n L4p L4n Bias Bias Vin Bias Vout M3n Bias Vin PSAT 22 dBm Measured BPSK OFDM Spectrum 16 25MHz POFDM 17 8 dBm Measured Transmit Constellation 64QAM 300kHz modulated signal OFDM Output Power dBm Measured Transmit Output Power 18 16 14 Carrier Leak Spectral Images 51dBc 12 10 29dBc 6 9 12 18 24 36 Data Rate Mbps 48 54 LNA Schematic Vdd Vout M3 Vin M4 M1 Lsp M2 Vin Lsn Receiver NF LNA to Baseband 8dB Programmable Baseband Ampli er Vdd Vdd Bias p VoutR2 Vin R1 Vout R2 VinBias n Vos Bias n offset control Vos Measured Receiver Performance IF Mixer Output dBm 10 0 10 Max Gain 20 30 40 Min Gain 50 60 90 80 70 60 50 40 30 20 10 RF Input dBm 0 Voltage Controlled Oscillator VCO Vc Control Control M1 M2 Phase Noise dBc Hz Composite Phase Noise at 5GHz 80 90 100 110 120 130 1k 10k 100k 1M Frequency Hz 10M Die Photograph Tx Synth Logic Rx Bias Measured Performance TX Output Power Level 22 dBm RX Chain Noise Figure 8 dB Phase Noise f 1MHz 112 dBc Hz Supply Voltages 2 5 V 3 3 V I O TX Chain Power Dissipation 790 mW RX Chain Power Dissipation 250 mW Synthesizer Power Dissipation 180 mW Technology 0 25 m 1P5M CMOS Package 64 pin LPCC Die Size 22 mm2 Conclusions IEEE 802 11a radio transceiver in 0 25 m standard digital CMOS for 5 GHz WLAN No external IF lter TX double image reject mixers RX very high IF of 1GHz Dual conversion with sliding IF single synthesizer Integration of transmitter with 22dBm output power receiver with 8dB noise gure synthesizer with 112dBc Hz f 1MHz Acknowledgement Support of the Wireless Team at Atheros for design layout and testing In particular H Dieh J Kung R Popescu A Ong J Zheng D Nakahira R Subramanian J Kuskin A Dao D Johnson C Lee L Thon P Husted W McFarland S Wong R Bahr T Meng Assistance of TSMC In particular S C Wong and B K Liew
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