Advanced VLSI Design Project VerificationWhat is VerificationCost of VerificationBasic IdeaForms of VerificationComponent VerificationSlide 7TestbenchSlide 9Memory VerificationCPU VerificationSlide 12ReferencesAdvanced VLSI Design ProjectVerificationBobby DixonELEC 7770-001What is Verification•Act of proving or disproving the correctness of a system with respect to strict specifications regarding the system•Process used to demonstrate functional correctness of a designCost of Verification•Can vary depending on form and method of verification•Also depends on what level of VLSI realization it is conductedCost of verification [1]Basic Idea•Given specifications, does design do what was specified?Forms of Verification•Simulation: verify selected cases of design functionality•Formal: exhaustively verifies all behavior of design•Used a mix of specification justification and functional demonstrationComponent Verification•During design phase each component drawn up according to specification•Specifications verified to meet requirements•Components to be exact replication of architecture specificationComponent Verification•Each component separately simulated•All input and output exhaustively tested•Functions checked and errors correctedTestbench•A virtual environment used to verify the correctness of a design•Create a circuit that will provide input stimuli for a design and check the output response for proper functionCUTTESTBENCHTestbench•Consists of four components:–Input: stimuli needed for testbench to function–Job: applies stimuli to model under test–Check: retrieves output and analyzes–Output: takes analysis and acts accordingly•Not part of actual designMemory Verification•Used testbench to verify memory component•Marched through address space writing and reading values to check functionMemoryTESTBENCHCPU Verification•Top level made up of every component plus the needed signals to connect and drive respective components•Formal verification at this level not an optionCPU Verification•Test program to functionally verify all possible CPU operations•Each operation’s output was checked for correctness100100100011000100111010111000011111000000011111110000011111111100000000CPUReferences•1. Dr. C. Stroud, ELEC 6970 Lecture 1 Auburn University, Fall 2006•2. Dr. V. Agrawal, ELEC 7770 Lecture 6 Auburn University, Spring
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