CPU ArchitectureInstruction FormatsIdea behind multicycle approachFive Execution StepsStep 1: Instruction FetchStep 2: Instruction Decode and Register FetchStep 3 (instruction dependent)Step 4 (R-type or memory-access)Step 5 (Write-back step)Summary:Slide 11CPU ArchitectureCPU ArchitectureWhy not single cycle?Why not single cycle?Hardware complexityHardware complexityWhy not pipelined?Why not pipelined?Time constraintsTime constraintsWhy multi-cycle?Why multi-cycle?Hardware reuseHardware reuseEase of implementationEase of implementationFormats:Formats:Address fields are not 32 bits Address fields are not 32 bits — — How do we handle this with load and store How do we handle this with load and store instructions?instructions?Instruction FormatsInstruction FormatsRIJopoprsrsrtrtrdrdshamtshamtfunctfunctopoprsrsrtrt16 bit address16 bit addressopop26 bit address26 bit addressIdea behind multicycle Idea behind multicycle approachapproachWe define each instruction from the ISA perspectiveWe define each instruction from the ISA perspectiveBreak it down into steps following our rule that data flows through at Break it down into steps following our rule that data flows through at most one major functional unit (e.g., balance work across steps)most one major functional unit (e.g., balance work across steps)Introduce new registers as needed (e.g, A, B, ALUOut, MDR, etc.)Introduce new registers as needed (e.g, A, B, ALUOut, MDR, etc.)Finally try and pack as much work into each step Finally try and pack as much work into each step (avoid unnecessary cycles)(avoid unnecessary cycles)while also trying to share steps where possiblewhile also trying to share steps where possible(minimizes control, helps to simplify solution)(minimizes control, helps to simplify solution)Result: Our multi-cycle Implementation!Result: Our multi-cycle Implementation!Instruction FetchInstruction FetchInstruction Decode and Register FetchInstruction Decode and Register FetchExecution, Memory Address Computation, or Branch CompletionExecution, Memory Address Computation, or Branch CompletionMemory Access or R-type instruction completionMemory Access or R-type instruction completionWrite-back stepWrite-back stepINSTRUCTIONS TAKE FROM 3 - 5 CYCLES!INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!Five Execution StepsFive Execution StepsUse PC to get instruction and put it in the Instruction Register.Use PC to get instruction and put it in the Instruction Register.Increment the PC by 4 and put the result back in the PC.Increment the PC by 4 and put the result back in the PC.Can be described succinctly using RTL "Register-Transfer Can be described succinctly using RTL "Register-Transfer Language"Language"IR <= Memory[PC];IR <= Memory[PC];PC <= PC + 4;PC <= PC + 4;What is the advantage of updating the PC now?What is the advantage of updating the PC now?Step 1: Instruction FetchStep 1: Instruction FetchRead registers rs and rt in case we need themRead registers rs and rt in case we need themCompute the branch address in case the instruction is a branchCompute the branch address in case the instruction is a branchRTL:RTL:A <= Reg[IR[25:21]];A <= Reg[IR[25:21]];B <= Reg[IR[20:16]];B <= Reg[IR[20:16]];ALUOut <= PC + (sign-extend(IR[15:0]) << 2);ALUOut <= PC + (sign-extend(IR[15:0]) << 2);We aren't setting any control lines based on the We aren't setting any control lines based on the instruction type instruction type (we are busy "decoding" it in our control logic)(we are busy "decoding" it in our control logic)Step 2: Instruction Decode Step 2: Instruction Decode and Register Fetchand Register FetchALU is performing one of three functions, based on ALU is performing one of three functions, based on instruction typeinstruction typeMemory Reference:Memory Reference:ALUOut <= A + sign-extend(IR[15:0]);ALUOut <= A + sign-extend(IR[15:0]);R-type:R-type:ALUOut <= A op B;ALUOut <= A op B;Branch:Branch:if (A==B) PC <= ALUOut;if (A==B) PC <= ALUOut;Step 3 (instruction Step 3 (instruction dependent)dependent)Loads and stores access memoryLoads and stores access memoryMDR <= Memory[ALUOut];MDR <= Memory[ALUOut];ororMemory[ALUOut] <= B;Memory[ALUOut] <= B;R-type instructions finishR-type instructions finishReg[IR[15:11]] <= ALUOut;Reg[IR[15:11]] <= ALUOut;The write actually takes place at the end of the cycle on the edgeThe write actually takes place at the end of the cycle on the edgeStep 4 (R-type or memory-Step 4 (R-type or memory-access)access)Reg[IR[20:16]] <= MDR;Reg[IR[20:16]] <= MDR;Step 5 (Write-back step)Step 5 (Write-back step)Summary:Summary:Complete Multi-Cycle DatapathText –Fig.