Timing Analysis for CPU Design ProjectELEC 7770-001 Advanced VLSI DesignDr. Vishwani D. Agrawal - Chaitanya BandiNeed for timing analysis:High-performance integrated circuits have traditionally been characterized by the clock frequency atwhich they operate. Delay calculation must be incorporated into the inner loop of timing optimizersat various phases of design, such as logic synthesis, layout (placement and routing), and in in-placeoptimizations performed later in the design cycle. While such timing measurements can theoreticallybe performed using a rigorous circuit simulation, such an approach is liable to be too slow to bepractical.Circuit Level Timing Constraints: Combinational LogicFlip-FlopInputsOutputsStateNext statePropagation delay through flip flopPropagation delayTwo kinds of timing errors are possible in such a system:- A hold time violation, when a signal arrives too early and advances one clock cycle before itshould.- A setup time violation, when a signal arrives too late, and misses the time when it shouldadvance. Tclkmin = tpFF + tpCL + tsuThe fastest clock that can operate on the circuit depends on the sum of the propagation timethrough the flip-flop, the propagation time through the Combinational logic, and the flip-flopsetup time (depends on the technology used).The above analysis could have been implemented by Quicksim II, but Quicksim and related tools areapparently no longer supported by Mentor Graphics. It is also the case that most of the timinganalysis models were not designed for the newest technologies (.18um) in the ASIC Design Kit. Atthis point, I would like to suggest that, instead of using tsmc018 technology, it is preferable to useami05 or any other older technologies that are supported by the timing analyzers. Design Flow:The expected design flow is to use ModelSim for functional verification of digital designs, with thecircuit modeled in VHDL and/or Verilog. This includes both behavioral models and gate-levelVHDL/Verilog netlists. A Verilog netlist is used as input to the chip layout "back end" tools. Afterconversion to a circuit-level netlist, Eldo and MachTA, both SPICE-based simulators, are available.Both can do mixed-signal simulation, but Eldo is better for analog simulation and MachTA moreefficient for large digital and Post-Layout simulations.Timing Analysis using Eldo: Extract the schematic from the Netlist. Export it as a Spice format. Force vectors to observe the critical path from the simulation results files. Find the critical path from the Waveform ViewerCritical Path from the Waveform finder is found by simulating the circuit and observing the behaviorof the output node that takes the longest time to produce a change on its line. The time from whichthe inputs change to the time at which the output on the critical path gives the maximum delay of thecircuit. This defines the maximum Clock frequency of the circuit.Post Layout Analysis: The Post layout incorporates both the block and routing delays as a final analysis of thedesign’s timing constraints. Post layout simulation is a better parameter to find the maximum operational frequency andbehavior of the circuit.Mach TA is used for Post-Layout timing analysis.Timing analysis from the Netlist:Leonardo generates the delays of the area optimized and delay optimized netlist. It also gives thecritical path on which this delay is defined. The delay of the area optimized netlist has a lesserdelay than that of the delay optimized netlist. Hence upon observing the delay of the areaoptimized netlist, the maximum clock frequency can be approximated. The delay of the Area Optimised Netlist of the CPU design is: 13.13 nsThe Maximum clock frequency at which it can be operated : 75.4 MHzThis is just an estimate of the pre-layout timing analysis. This delay may differ based on the levelof optimization.References: 1. Dr. V. P. Nelson, Tutorial Documents for Mentor Graphics Tools, http://www.eng.auburn.edu/department/ee/mgc/mentor.html2. Dr. V. P. Nelson, Elec 5250/6250 Lecture 3,6, 7&22 Auburn University, Fall 2006 3. Dr. V. Agrawal, Elec 7770 Lecture 14 Auburn University, Spring 2007AppendixForce values for the Spice Simulation: *option definition.option modwl noascii engnot aex alignext** .CONNECT statements*.CONNECT GND 0* ELDO netlist generated with ICnet by 'neelisa' on Wed Apr 25 2007 at 18:47:30** Globals.*.global GND VDD* source statementsvdd vdd gnd dc 2.5v ! supply voltage valuevclk Clock ac 1 pwl(0 0 10n 0 10.1n 5 20n 5 20.1n 0 30n 0 30.1n 5 40n 5 40.1n 0 50n 0 50.1n 5 60n5 60.1n 0 70n 0 70.1n 5 80n 5 80.1n 0 90n 0 90.1n 5 100n 5 100.1n 0 110n 0 110.1n 5 120n 5 120.1n0)vmemout1 MEMORY_OUTPUT[1]ac 1 pwl(0 0 10n 0 10.1n 5 30n 5 30.1n 0 120n 0)vmemout2 MEMORY_OUTPUT[2] ac 1 pwl(0 0 10n 0 10.1n 5 50n 5 50.1n 0 120n 0)vmemout3 MEMORY_OUTPUT[3] ac 1 pwl(0 0 10n 0 10.1n 5 70n 5 70.1n 0 120n 0)vmemout10 MEMORY_OUTPUT[10] ac 1 pwl(0 0 10n 0 10.1n 5 90n 5 90.1n 0 120n 0)vmemout0 MEMORY_OUTPUT[0] gnd dc 5vvmemout4 MEMORY_OUTPUT[4] gnd dc 5vvmemout5 MEMORY_OUTPUT[5] gnd dc 5vvmemout6 MEMORY_OUTPUT[6] gnd dc 5vvmemout7 MEMORY_OUTPUT[7] gnd dc 5vvmemout8 MEMORY_OUTPUT[8] gnd dc 5vvmemout9 MEMORY_OUTPUT[9] gnd dc 5vvmemout11 MEMORY_OUTPUT[11] gnd dc 5vvmemout12 MEMORY_OUTPUT[12] gnd dc 5vvmemout13 MEMORY_OUTPUT[13] gnd dc 5vvmemout14 MEMORY_OUTPUT[14] gnd dc 5vvmemout15 MEMORY_OUTPUT[15] gnd dc 5vvinr0 INR[0] gnd dc 5vvinr1 INR[1] gnd dc 5vvinr2 INR[2] gnd dc 5vvinr3 INR[3] gnd dc 5vvreset RESET ac 1 pwl(0 5 10n 5 10.1n 0 120n 0)** lib.LIB $ADK/technology/ic/models/tsmc018.mod** analysis!.ac.tran 1n 200n ! from 0 to 200ns by step 1ns.** output.plot tran v(outvalue[0]) v(outvalue[1]) v(outvalue[2]) v(outvalue[3]) v(outvalue[4]) v(outvalue[5])v(outvalue[6])+ v(outvalue[7]) v(outvalue[8]) v(outvalue[9]) v(outvalue[10]) v(outvalue[11]) v(outvalue[12])v(outvalue[13]) v(outvalue[14])+ v(outvalue[15]) v(outvalue[16]) v(outvalue[17]) v(outvalue[18]) v(outvalue[19]) v(outvalue[20])v(outvalue[21]) v(outvalue[22])+ v(outvalue[23]) v(outvalue[24]) v(outvalue[25]) v(outvalue[26]) v(outvalue[27]) v(outvalue[28])v(outvalue[29]) v(outvalue[30])+ v(outvalue[31]) v(memory_address[0]) v(memory_address[1]) v(memory_address[2])v(memory_address[3]) v(memory_address[4]) + v(memory_address[5]) v(memory_address[6]) v(memory_address[7]) v(memory_data[0])v(memory_data[1])