ELEC 7770 Advanced VLSI Design Spring 2007 SOC Test SchedulingPower Considerations in DesignTesting Differs from Functional OperationBasic Mode of TestingFunctional Inputs vs. Test VectorsAn ExampleReducing Comb. Test PowerOpen-Loop TSPTraveling Salesperson ProblemScan TestingExample: State MachineScan Testing of State MachineLow Power Scan Flip-FlopBuilt-In Self-Test (BIST)Test Scheduling ExampleBIST Configuration 1: Test TimeBIST Configuration 2: Test PowerTesting of MCM and SOCResource Allocation GraphTest Compatibility Graph (TCG)Test Scheduling AlgorithmTest Scheduling Algorithm . . .TS Algorithm: Cover TableA System Example: ASIC Z*Test Scheduling for ASIC ZReferencesSpring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2007Spring 2007SOC Test SchedulingSOC Test SchedulingVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07Spring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22Power Considerations in DesignPower Considerations in DesignA circuit is designed for certain function. Its design must A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that allow the power consumption necessary to execute that function.function.Power buses are laid out to carry the maximum current Power buses are laid out to carry the maximum current necessary for the function.necessary for the function.Heat dissipation of package conforms to the average Heat dissipation of package conforms to the average power consumption during the intended function.power consumption during the intended function.Layout design and verification must account for “hot Layout design and verification must account for “hot spots” and “voltage droop” – delay, coupling noise, weak spots” and “voltage droop” – delay, coupling noise, weak signals.signals.Spring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33Testing Differs from Functional Testing Differs from Functional OperationOperationVLSI chipsystemSysteminputsSystemoutputsFunctional inputsFunctional outputsOther chipsSpring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44Basic Mode of TestingBasic Mode of TestingVLSI chipTest vectors:Pre-generated and stored inATEDUT output for comparison with expected response stored in ATEAutomatic Test Equipment (ATE):Control processor, vector memory,timing generators, power module,response comparatorPowerClockPackaged or unpackaged device under test (DUT)Spring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55Functional Inputs vs. Test VectorsFunctional Inputs vs. Test VectorsFunctional inputs:Functional inputs:Functionally meaningful Functionally meaningful signalssignalsGenerated by circuitryGenerated by circuitryRestricted set of inputsRestricted set of inputsMay have been May have been optimized to reduce optimized to reduce logic activity and powerlogic activity and powerTest vectors:Test vectors:Functionally irrelevant Functionally irrelevant signalssignalsGenerated by software Generated by software to test faultsto test faultsCan be random or Can be random or pseudorandompseudorandomMay be optimized to May be optimized to reduce test time; can reduce test time; can have high logic activityhave high logic activityMay use testability logic May use testability logic for test applicationfor test applicationSpring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66An ExampleAn ExampleVLSI chipBinary to decimal converter3-bit random vectors8-bit1-hot vectorsVLSI chipsystemVLSI chip in system operationVLSI chip under testHigh activity8-bit test vectors from ATESpring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Reducing Comb. Test Power Reducing Comb. Test Power 1 1 0 0 01 0 1 0 01 0 1 0 11 0 1 1 1V1 V2 V3V4 V53 413223211V1 V2 V3 V4 V510 input transitionsTraveling salesperson problem (TSP): Find the shortest distance closed path (or cycle) to visit all nodes exactly once.V1 V3 V5 V4 V21 0 0 0 11 1 0 0 01 1 1 0 01 1 1 1 05 input transitionsSpring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Open-Loop TSP Open-Loop TSP Add a node V0 at distance 0 from all other nodes.Add a node V0 at distance 0 from all other nodes.Solve TSP for the new graph.Solve TSP for the new graph.Delete V0 from the solution.Delete V0 from the solution.V1 V2 V3V4 V53 413223211V000000Spring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99Traveling Salesperson ProblemTraveling Salesperson ProblemA. V. Aho, J. E. Hopcroft anf J. D. Ullman, A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Data Structures and AlgorithmsStructures and Algorithms, Reading, , Reading, Massachusetts: Addison-Wesley, 1983.Massachusetts: Addison-Wesley, 1983.E. Horowitz and S. Sahni, E. Horowitz and S. Sahni, Fundamentals of Fundamentals of Computer AlgorithmsComputer Algorithms, Computer Science Press, , Computer Science Press, 1984.1984.Spring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1010Scan TestingScan TestingCombinational logicScan flip- flopsPrimary inputsPrimary outputsScan-inSIScan-outSOScan enableSEDFFmuxSESIDDD’D’SO10Spring 07, Jan 30Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1111Example: State MachineExample: State MachineS5S1S4S2S3Reduced power state encodingS1 = 000S2 = 011S3 = 001S4 = 010S5 = 100State transitionState transitionComb. Input Comb. Input changeschanges000 → 001000 → 00111000 → 100000 → 10011011 → 010011