ELEC 7770 Advanced VLSI Design Spring 2007 Power Consumption in a MemoryMemory ArchitectureMemory OrganizationAn SRAM CellRead OperationPrecharge CircuitReading 1 from CellWrite Operation, bit = 1→ 0Cell Array Power ManagementSense AmplifierBlock-Oriented ArchitectureHierarchical OrganizationPower SavingStatic PowerAdding Resistance in Leakage PathLowering Supply VoltageParallelization of MemoriesReferencesSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2007Spring 2007 Power Consumption in a MemoryPower Consumption in a MemoryVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07Spring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22Memory ArchitectureMemory ArchitectureWord 0Word 1Word 2M bitsStorage cellWord N-2Word N-1Input-Output (M bits)N wordsS0SN-1Word 0Word 1Word 2M bitsStorage cellWord N-2Word N-1Input-Output (M bits)N wordsS0SN-1A0A1.Ak-1Decoder k address lines k = log2NSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33Memory OrganizationMemory OrganizationSense amplifiers/driversColumn decoderAKAK-1AL-1Storage cellWord lineBit lineInput-Output (M bits)A0AK-12L-KM.2KSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44An SRAM CellAn SRAM CellbitbitVDDWLBLBLSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55Read OperationRead OperationbitbitVDDWLBLBL1. Precharge to VDD2. WL = Logic 13. Sense amplifier converts BL swing to logic levelSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Precharge CircuitPrecharge CircuitbitbitVDDWLBLBLDiff. sense ampl.VDDVDDPCSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Reading 1 from CellReading 1 from CellPrecharge timeWLBLBLSense ampl. outputSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Write Operation, bit = 1Write Operation, bit = 1→ 0→ 0bitbitVDDWLBLBL011. Set BL = 0, BL = 12. WL = 1Spring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99Cell Array Power ManagementCell Array Power ManagementSmaller transistorsSmaller transistorsLow supply voltageLow supply voltageLower voltage swing (0.1V – 0.3V for SRAM)Lower voltage swing (0.1V – 0.3V for SRAM)Sense amplifier restores the full voltage swing for Sense amplifier restores the full voltage swing for outside use.outside use.Spring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1010Sense AmplifierSense Amplifierbit bitSESense ampl. enable:Low when bit lines are precharged and equalizedVDDFull voltage swing outputSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1111Block-Oriented ArchitectureBlock-Oriented ArchitectureA single cell array may contain 64 Kbits to 256 A single cell array may contain 64 Kbits to 256 Kbits.Kbits.Larger arrays become slow and consume more Larger arrays become slow and consume more power.power.Larger memories are block oriented.Larger memories are block oriented.Spring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1212Hierarchical OrganizationHierarchical OrganizationGlobal data busGlobal amplifier/driverI/O Block 0 Block 1 Block P-1ControlcircuitryBlock selectorRow addr.Column addr.Block addr.Spring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1313Power SavingPower SavingBlock-oriented memoryBlock-oriented memoryLengths of local word and bit lines are kept small.Lengths of local word and bit lines are kept small.Block address is used to activate the addressed Block address is used to activate the addressed block.block.Unaddressed blocks are put in power-saving mode:Unaddressed blocks are put in power-saving mode: sense amplifier and row/column decoders are sense amplifier and row/column decoders are disabled.disabled.Power is maintained for data retention in cells.Power is maintained for data retention in cells.Spring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1414Static PowerStatic Power0.0 0.6 1.2 1.8Supply voltage1.3μ1.1μ900n700n500n300n100n0.13μ CMOS0.18μ CMOS8-kbit SRAM7x increaseLeakage current (Amperes)Spring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1515Adding Resistance in Leakage PathAdding Resistance in Leakage PathSRAM cell arraySRAM cell arraySRAM cell arrayGNDVDDsleepsleepLow-threshold transistorVSS.intVDD.intSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1616Lowering Supply VoltageLowering Supply VoltageSRAM cell arraySRAM cell arraySRAM cell arrayGNDVDDsleepVDDL= 100mV for 0.13μ CMOSSleep = 1, data retention modeSpring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1717Parallelization of MemoriesParallelization of Memories instr. A instr. C instr. E...f/2Mem 1 instr. B instr. D instr. F...f/2Mem 2MUXf/20 1Power = C’ f/2 VDD2C. Piguet, “Circuit and Logic Level Design,” pp. 124-125 inW. Nebel and J. Mermet (Eds.), Low Power Design in DeepSubmocron Electronics, Springer, 1997.Spring 07, Feb 27Spring 07, Feb 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1818ReferencesReferencesK. Itoh, K. Itoh, VLSI Memory Chip DesignVLSI Memory Chip Design, Springer-, Springer-Verlag, 2001.Verlag, 2001.J. M. Rabaey, A. Chandrakasan and B. Nikolić, J. M. Rabaey, A. Chandrakasan and B. Nikolić,