ELEC 7770 Advanced VLSI Design Spring 2008 Timing Simulation and STADigital Circuit TimingTiming Analysis and OptimizationCircuit DelaysSpiceLogic Model of MOS CircuitSpice CharacterizationSpice Characterization (Cont.)Complex Gates: Switch-Level PartitionsInterconnect Delay: Elmore Delay ModelElmore Delay FormulaEvent Propagation DelaysCircuit OutputsDelay and Discrete-Event Simulation (NAND gate)Event-Driven Simulation (Example)Time Wheel (Circular Stack)Timing Design and Delay TestStatic Timing Analysis (STA)Early ReferencesBasic IdeasA Gantt Chart in Microsoft ExcelUsing a Gantt ChartPert ChartExample: Thesis ResearchCritical PathA Basic Timing Analysis AlgorithmExampleExample (Cont.)Slide 29Finding Earliest and Longest TimesShortest and Longest PathsCharacteristics of STAAlgorithms for Directed Acyclic Graphs (DAG)ReferencesSpring 08, Jan 31 . .Spring 08, Jan 31 . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2008Spring 2008 Timing Simulation and STA Timing Simulation and STAVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn University, Auburn, AL 36849ECE Department, Auburn University, Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlSpring 08, Jan 31 . .Spring 08, Jan 31 . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22Digital Circuit TimingDigital Circuit TimingInputsOutputstimeTransientregionClock periodComb.logicOutputObservationinstantInputSignalchangesSynchronizedWith clockSpring 08, Jan 31 . .Spring 08, Jan 31 . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33Timing Analysis and OptimizationTiming Analysis and OptimizationTiming analysisTiming analysisDynamic analysis: Simulation.Dynamic analysis: Simulation.Static timing analysis (STA): Vector-less topological analysis of Static timing analysis (STA): Vector-less topological analysis of circuit.circuit.Timing optimizationTiming optimizationPerformancePerformanceClock designClock designOther forms of design optimizationOther forms of design optimizationChip areaChip areaTestabilityTestabilityPowerPowerSpring 08, Jan 31 . .Spring 08, Jan 31 . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44Circuit DelaysCircuit DelaysSwitching or inertial delay is the interval between input Switching or inertial delay is the interval between input change and output change of a gate:change and output change of a gate:Depends on input capacitance, device (transistor) Depends on input capacitance, device (transistor) characteristics and output capacitance of gate.characteristics and output capacitance of gate.Also depends on input rise or fall times and states of other Also depends on input rise or fall times and states of other inputs (second-order effects).inputs (second-order effects).Approximation: fixed rise and fall delays (or min-max delay Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output.range, or single fixed delay) for gate output.Propagation or interconnect delay is the time a transition Propagation or interconnect delay is the time a transition takes to travel between gates:takes to travel between gates:Depends on transmission line effects (distributed Depends on transmission line effects (distributed RR, , LL, , CC parameters, length and loading) of routing paths.parameters, length and loading) of routing paths.Approximation: modeled as lumped delays for gate inputs.Approximation: modeled as lumped delays for gate inputs.Spring 08, Jan 31 . .Spring 08, Jan 31 . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55SpiceSpiceCircuit/device level analysisCircuit/device level analysisCircuit modeled as network of transistors, capacitors, Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources.resistors and voltage/current sources.Node current equations using Kirchhoff’s current law.Node current equations using Kirchhoff’s current law.Analysis is accurate but expensiveAnalysis is accurate but expensiveUsed to characterize parts of a larger circuit.Used to characterize parts of a larger circuit.Original references:Original references:L. W. Nagel and D. O. Pederson, “SPICE – Simulation L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr. M382, EECS Dept., University of California, Berkeley, Apr. 1973.1973.L. W. Nagel, L. W. Nagel, SPICE 2, A Computer program to Simulate SPICE 2, A Computer program to Simulate Semiconductor CircuitsSemiconductor Circuits, PhD Dissertation, University of , PhD Dissertation, University of California, Berkeley, May 1975.California, Berkeley, May 1975.Spring 08, Jan 31 . .Spring 08, Jan 31 . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Ca Logic Model of MOS CircuitLogic Model of MOS CircuitCc Cb VDD a b c pMOS FETsnMOSFETsCa , Cb , Cc and Cd are node capacitancesDcDacab Da and Db are interconnect or propagation delays Dc is inertial delayof gateDbCdSpring 08, Jan 31 . .Spring 08, Jan 31 . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Spice CharacterizationSpice CharacterizationInput data patternInput data patternDelay (ps)Delay (ps)Dynamic energy (pJ)Dynamic energy (pJ) aa = = bb = 0 → 1 = 0 → 169691.551.55 aa = 1, = 1, bb = 0 → 1 = 0 → 162621.671.67 aa = 0 → 1, = 0 → 1, bb = 1 = 150501.721.72aa = = bb = 1 → 0 = 1 → 035351.821.82aa = 1, = 1, bb = 1 → 0 = 1 → 076761.391.39aa = 1 → 0, = 1 → 0, bb = 1 = 157571.941.94Spring 08, Jan 31 . .Spring 08, Jan 31 . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Spice Characterization (Cont.)Spice Characterization (Cont.)Input data patternInput data patternStatic power (pW)Static power (pW) aa = = bb = 0 = 05.055.05 aa = 0, = 0, bb = 1 = 113.113.1aa = 1, = 1, bb = 0 = 05.105.10aa = = bb = 1 = 128.528.5Spring 08, Jan 31 .