ELEC 7770 Advanced VLSI Design Spring 2007 VLSI System DFTSOC Design: A DFT ProblemConventional Test: In-Circuit Test (ICT)PCB vs. SOCSOC: Core-Based DesignPartitioning for TestTest-Wrapper for a CoreA Test-WrapperReferencesOverhead of Test AccessOverhead EstimateDFT Architecture for SOCDFT ComponentsRelated TopicsSummarySpring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2007Spring 2007VLSI System DFTVLSI System DFTVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07Spring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22SOC Design: A DFT ProblemSOC Design: A DFT ProblemGiven the changing scenario in VLSI:Given the changing scenario in VLSI:Mixed-signal circuitsMixed-signal circuitsSystem-on-a-chipSystem-on-a-chipMulti-chip modulesMulti-chip modulesIntellectual propertyIntellectual property (IP) cores (IP) coresA system must be designed for testability. A system must be designed for testability.Spring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33Conventional Test:Conventional Test:In-Circuit Test (ICT)In-Circuit Test (ICT)A bed-of-nails fixture provides direct access to each chip on A bed-of-nails fixture provides direct access to each chip on the board.the board.Advantages: Thorough test for devices; good interconnect Advantages: Thorough test for devices; good interconnect test.test.Limitations:Limitations:Works best when analog and digital functions are implemented on Works best when analog and digital functions are implemented on separate chips.separate chips.Devices must be designed for backdriving protection.Devices must be designed for backdriving protection.Not applicable to system-on-a-chip (SOC).Not applicable to system-on-a-chip (SOC).Disadvantages:Disadvantages:High cost and inflexibility of test fixture.High cost and inflexibility of test fixture.System test must check for timing.System test must check for timing.Spring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44PCB vs. SOCPCB vs. SOCTested partsTested partsIn-circuit test (ICT)In-circuit test (ICT)Easy test accessEasy test accessBulkyBulkySlowSlowHigh assembly costHigh assembly costHigh reliabilityHigh reliabilityFast interconnectsFast interconnectsLow costLow costUntested coresUntested coresNo internal test accessNo internal test accessMixed-signal devicesMixed-signal devicesPCB SOCSpring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55SOC: Core-Based DesignSOC: Core-Based DesignCores are predesigned and verified but Cores are predesigned and verified but untested blocks:untested blocks:Soft core (synthesizable RTL)Soft core (synthesizable RTL)Firm core (gate-level netlist)Firm core (gate-level netlist)Hard core (non-modifiable layout, often called Hard core (non-modifiable layout, often called legacy corelegacy core))Core is the intellectual property of vendor Core is the intellectual property of vendor (internal details not available to user.)(internal details not available to user.)Core-vendor supplied tests must be applied Core-vendor supplied tests must be applied to embedded cores.to embedded cores.Spring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Partitioning for TestPartitioning for TestPartition according to test methodology:Partition according to test methodology:Logic blocksLogic blocksMemory blocksMemory blocksAnalog blocksAnalog blocksProvide test access:Provide test access:Boundary scanBoundary scanAnalog test busAnalog test busProvide test-wrappers (also called collars) Provide test-wrappers (also called collars) for cores.for cores.Spring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Test-Wrapper for a CoreTest-Wrapper for a CoreTest-wrapper (or collar) is the logic added around a core to Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core.provide test access to the embedded core.Test-wrapper provides:Test-wrapper provides:For each core input terminalFor each core input terminalA normal mode – Core terminal driven by host chipA normal mode – Core terminal driven by host chipAn external test mode – Wrapper element observes core input An external test mode – Wrapper element observes core input terminal for interconnect testterminal for interconnect testAn internal test mode – Wrapper element controls state of core An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside coreinput terminal for testing the logic inside coreFor each core output terminalFor each core output terminalA normal mode – Host chip driven by core terminalA normal mode – Host chip driven by core terminalAn external test mode – Host chip is driven by wrapper element for An external test mode – Host chip is driven by wrapper element for interconnect testinterconnect testAn internal test mode – Wrapper element observes core outputs An internal test mode – Wrapper element observes core outputs for core testfor core testSpring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88A Test-WrapperA Test-WrapperWrappertestcontroller Scan chain Scan chain Scan chain to/from TAPfrom/toExternalTest pinsWrapperelementsCoreFunctionalcore inputsFunctionalcore outputsSpring 07, Jan 25Spring 07, Jan 25ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99ReferencesReferencesTest Wrapper:Test Wrapper:B. Nadeau-Dosti, B. Nadeau-Dosti, Design for At-Speed Test, Diagnosis Design for At-Speed Test, Diagnosis and Measurementand Measurement, Springer, 2000.,